DMASequencer.cc revision 6368:cecc7019b458 
1
2#include "mem/ruby/system/DMASequencer.hh"
3#include "mem/ruby/buffers/MessageBuffer.hh"
4#include "mem/ruby/slicc_interface/AbstractController.hh"
5
6/* SLICC generated types */
7#include "mem/protocol/DMARequestMsg.hh"
8#include "mem/protocol/DMARequestType.hh"
9#include "mem/protocol/DMAResponseMsg.hh"
10#include "mem/ruby/system/System.hh"
11
12DMASequencer::DMASequencer(const string & name)
13  : RubyPort(name)
14{
15}
16
17void DMASequencer::init(const vector<string> & argv)
18{
19  m_version = -1;
20  m_controller = NULL;
21  for (size_t i=0;i<argv.size();i+=2) {
22    if (argv[i] == "controller")
23      m_controller = RubySystem::getController(argv[i+1]);
24    else if (argv[i] == "version")
25      m_version = atoi(argv[i+1].c_str());
26  }
27  assert(m_controller != NULL);
28  assert(m_version != -1);
29
30  m_mandatory_q_ptr = m_controller->getMandatoryQueue();
31  m_is_busy = false;
32  m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
33}
34
35int64_t DMASequencer::makeRequest(const RubyRequest & request)
36{
37  uint64_t paddr = request.paddr;
38  uint8_t* data = request.data;
39  int len = request.len;
40  bool write = false;
41  switch(request.type) {
42  case RubyRequestType_LD:
43    write = false;
44    break;
45  case RubyRequestType_ST:
46    write = true;
47    break;
48  case RubyRequestType_NULL:
49  case RubyRequestType_IFETCH:
50  case RubyRequestType_RMW:
51    assert(0);
52  }
53
54  assert(!m_is_busy);  // only support one outstanding DMA request
55  m_is_busy = true;
56
57  active_request.start_paddr = paddr;
58  active_request.write = write;
59  active_request.data = data;
60  active_request.len = len;
61  active_request.bytes_completed = 0;
62  active_request.bytes_issued = 0;
63  active_request.id = makeUniqueRequestID();
64
65  DMARequestMsg msg;
66  msg.getPhysicalAddress() = Address(paddr);
67  msg.getLineAddress() = line_address(msg.getPhysicalAddress());
68  msg.getType() = write ? DMARequestType_WRITE : DMARequestType_READ;
69  msg.getOffset() = paddr & m_data_block_mask;
70  msg.getLen() = (msg.getOffset() + len) <= RubySystem::getBlockSizeBytes() ?
71    len :
72    RubySystem::getBlockSizeBytes() - msg.getOffset();
73  if (write) {
74    msg.getType() = DMARequestType_WRITE;
75    msg.getDataBlk().setData(data, msg.getOffset(), msg.getLen());
76  } else {
77    msg.getType() = DMARequestType_READ;
78  }
79  m_mandatory_q_ptr->enqueue(msg);
80  active_request.bytes_issued += msg.getLen();
81
82  return active_request.id;
83}
84
85void DMASequencer::issueNext()
86{
87  assert(m_is_busy == true);
88  active_request.bytes_completed = active_request.bytes_issued;
89  if (active_request.len == active_request.bytes_completed) {
90    m_hit_callback(active_request.id);
91    m_is_busy = false;
92    return;
93  }
94
95  DMARequestMsg msg;
96  msg.getPhysicalAddress() = Address(active_request.start_paddr +
97				     active_request.bytes_completed);
98  assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
99  msg.getLineAddress() = line_address(msg.getPhysicalAddress());
100  msg.getOffset() = 0;
101  msg.getType() = (active_request.write ? DMARequestType_WRITE :
102		   DMARequestType_READ);
103  msg.getLen() = (active_request.len -
104		  active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
105		  active_request.len - active_request.bytes_completed :
106		  RubySystem::getBlockSizeBytes());
107  if (active_request.write) {
108    msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed],
109			     0, msg.getLen());
110    msg.getType() = DMARequestType_WRITE;
111  } else {
112    msg.getType() = DMARequestType_READ;
113  }
114  m_mandatory_q_ptr->enqueue(msg);
115  active_request.bytes_issued += msg.getLen();
116}
117
118void DMASequencer::dataCallback(const DataBlock & dblk)
119{
120  assert(m_is_busy == true);
121  int len = active_request.bytes_issued - active_request.bytes_completed;
122  int offset = 0;
123  if (active_request.bytes_completed == 0)
124    offset = active_request.start_paddr & m_data_block_mask;
125  assert( active_request.write == false );
126  memcpy(&active_request.data[active_request.bytes_completed],
127	 dblk.getData(offset, len), len);
128  issueNext();
129}
130
131void DMASequencer::ackCallback()
132{
133  issueNext();
134}
135
136void DMASequencer::printConfig(ostream & out)
137{
138
139}
140