DMASequencer.cc revision 6355:79464d8a4d2f 
1
2#include "mem/ruby/system/DMASequencer.hh"
3#include "mem/ruby/buffers/MessageBuffer.hh"
4#include "mem/ruby/slicc_interface/AbstractController.hh"
5
6/* SLICC generated types */
7#include "mem/protocol/DMARequestMsg.hh"
8#include "mem/protocol/DMARequestType.hh"
9#include "mem/protocol/DMAResponseMsg.hh"
10#include "mem/ruby/system/System.hh"
11
12DMASequencer::DMASequencer(const string & name)
13  : RubyPort(name)
14{
15}
16
17void DMASequencer::init(const vector<string> & argv)
18{
19  m_version = -1;
20  m_controller = NULL;
21  for (size_t i=0;i<argv.size();i+=2) {
22    if (argv[i] == "controller")
23      m_controller = RubySystem::getController(argv[i+1]);
24    else if (argv[i] == "version")
25      m_version = atoi(argv[i+1].c_str());
26  }
27  assert(m_controller != NULL);
28  assert(m_version != -1);
29
30  m_mandatory_q_ptr = m_controller->getMandatoryQueue();
31  m_is_busy = false;
32}
33
34int64_t DMASequencer::makeRequest(const RubyRequest & request)
35{
36  uint64_t paddr = request.paddr;
37  uint8_t* data = request.data;
38  int len = request.len;
39  bool write = false;
40  switch(request.type) {
41  case RubyRequestType_LD:
42    write = false;
43    break;
44  case RubyRequestType_ST:
45    write = true;
46    break;
47  case RubyRequestType_NULL:
48  case RubyRequestType_IFETCH:
49  case RubyRequestType_Locked_Read:
50  case RubyRequestType_Locked_Write:
51  case RubyRequestType_RMW_Read:
52  case RubyRequestType_RMW_Write:
53    assert(0);
54  }
55
56  assert(!m_is_busy);
57  m_is_busy = true;
58
59  active_request.start_paddr = paddr;
60  active_request.write = write;
61  active_request.data = data;
62  active_request.len = len;
63  active_request.bytes_completed = 0;
64  active_request.bytes_issued = 0;
65  active_request.id = makeUniqueRequestID();
66
67  DMARequestMsg msg;
68  msg.getPhysicalAddress() = Address(paddr);
69  msg.getType() = write ? DMARequestType_WRITE : DMARequestType_READ;
70  msg.getOffset() = paddr & RubyConfig::dataBlockMask();
71  msg.getLen() = (msg.getOffset() + len) < RubySystem::getBlockSizeBytes() ?
72    (msg.getOffset() + len) :
73    RubySystem::getBlockSizeBytes() - msg.getOffset();
74  if (write) {
75    msg.getType() = DMARequestType_WRITE;
76    msg.getDataBlk().setData(data, 0, msg.getLen());
77  } else {
78    msg.getType() = DMARequestType_READ;
79  }
80  m_mandatory_q_ptr->enqueue(msg);
81  active_request.bytes_issued += msg.getLen();
82
83  return active_request.id;
84}
85
86void DMASequencer::issueNext()
87{
88  assert(m_is_busy == true);
89  active_request.bytes_completed = active_request.bytes_issued;
90  if (active_request.len == active_request.bytes_completed) {
91    m_hit_callback(active_request.id);
92    m_is_busy = false;
93    return;
94  }
95
96  DMARequestMsg msg;
97  msg.getPhysicalAddress() = Address(active_request.start_paddr + active_request.bytes_completed);
98  assert((msg.getPhysicalAddress().getAddress() & RubyConfig::dataBlockMask()) == 0);
99  msg.getOffset() = 0;
100  msg.getType() = active_request.write ? DMARequestType_WRITE : DMARequestType_READ;
101  msg.getLen() = active_request.len - active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
102    active_request.len - active_request.bytes_completed :
103    RubySystem::getBlockSizeBytes();
104  if (active_request.write) {
105    msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed], 0, msg.getLen());
106    msg.getType() = DMARequestType_WRITE;
107  } else {
108    msg.getType() = DMARequestType_READ;
109  }
110  m_mandatory_q_ptr->enqueue(msg);
111  active_request.bytes_issued += msg.getLen();
112}
113
114void DMASequencer::dataCallback(const DataBlock & dblk)
115{
116  assert(m_is_busy == true);
117  int len = active_request.bytes_issued - active_request.bytes_completed;
118  int offset = 0;
119  if (active_request.bytes_completed == 0)
120    offset = active_request.start_paddr & RubyConfig::dataBlockMask();
121  memcpy(&active_request.data[active_request.bytes_completed], dblk.getData(offset, len), len);
122  issueNext();
123}
124
125void DMASequencer::ackCallback()
126{
127  issueNext();
128}
129
130void DMASequencer::printConfig(ostream & out)
131{
132
133}
134