DMASequencer.cc revision 11443
1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <memory> 30 31#include "debug/RubyDma.hh" 32#include "debug/RubyStats.hh" 33#include "mem/protocol/SequencerMsg.hh" 34#include "mem/protocol/SequencerRequestType.hh" 35#include "mem/ruby/system/DMASequencer.hh" 36#include "mem/ruby/system/RubySystem.hh" 37 38DMASequencer::DMASequencer(const Params *p) 39 : RubyPort(p) 40{ 41} 42 43void 44DMASequencer::init() 45{ 46 RubyPort::init(); 47 m_is_busy = false; 48 m_data_block_mask = mask(RubySystem::getBlockSizeBits()); 49 50 for (const auto &s_port : slave_ports) 51 s_port->sendRangeChange(); 52} 53 54RequestStatus 55DMASequencer::makeRequest(PacketPtr pkt) 56{ 57 if (m_is_busy) { 58 return RequestStatus_BufferFull; 59 } 60 61 Addr paddr = pkt->getAddr(); 62 uint8_t* data = pkt->getPtr<uint8_t>(); 63 int len = pkt->getSize(); 64 bool write = pkt->isWrite(); 65 66 assert(!m_is_busy); // only support one outstanding DMA request 67 m_is_busy = true; 68 69 active_request.start_paddr = paddr; 70 active_request.write = write; 71 active_request.data = data; 72 active_request.len = len; 73 active_request.bytes_completed = 0; 74 active_request.bytes_issued = 0; 75 active_request.pkt = pkt; 76 77 std::shared_ptr<SequencerMsg> msg = 78 std::make_shared<SequencerMsg>(clockEdge()); 79 msg->getPhysicalAddress() = paddr; 80 msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress()); 81 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; 82 int offset = paddr & m_data_block_mask; 83 84 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? 85 len : RubySystem::getBlockSizeBytes() - offset; 86 87 if (write && (data != NULL)) { 88 if (active_request.data != NULL) { 89 msg->getDataBlk().setData(data, offset, msg->getLen()); 90 } 91 } 92 93 assert(m_mandatory_q_ptr != NULL); 94 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); 95 active_request.bytes_issued += msg->getLen(); 96 97 return RequestStatus_Issued; 98} 99 100void 101DMASequencer::issueNext() 102{ 103 assert(m_is_busy); 104 active_request.bytes_completed = active_request.bytes_issued; 105 if (active_request.len == active_request.bytes_completed) { 106 // 107 // Must unset the busy flag before calling back the dma port because 108 // the callback may cause a previously nacked request to be reissued 109 // 110 DPRINTF(RubyDma, "DMA request completed\n"); 111 m_is_busy = false; 112 ruby_hit_callback(active_request.pkt); 113 return; 114 } 115 116 std::shared_ptr<SequencerMsg> msg = 117 std::make_shared<SequencerMsg>(clockEdge()); 118 msg->getPhysicalAddress() = active_request.start_paddr + 119 active_request.bytes_completed; 120 121 assert((msg->getPhysicalAddress() & m_data_block_mask) == 0); 122 msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress()); 123 124 msg->getType() = (active_request.write ? SequencerRequestType_ST : 125 SequencerRequestType_LD); 126 127 msg->getLen() = 128 (active_request.len - 129 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 130 active_request.len - active_request.bytes_completed : 131 RubySystem::getBlockSizeBytes()); 132 133 if (active_request.write) { 134 msg->getDataBlk(). 135 setData(&active_request.data[active_request.bytes_completed], 136 0, msg->getLen()); 137 } 138 139 assert(m_mandatory_q_ptr != NULL); 140 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); 141 active_request.bytes_issued += msg->getLen(); 142 DPRINTF(RubyDma, 143 "DMA request bytes issued %d, bytes completed %d, total len %d\n", 144 active_request.bytes_issued, active_request.bytes_completed, 145 active_request.len); 146} 147 148void 149DMASequencer::dataCallback(const DataBlock & dblk) 150{ 151 assert(m_is_busy); 152 int len = active_request.bytes_issued - active_request.bytes_completed; 153 int offset = 0; 154 if (active_request.bytes_completed == 0) 155 offset = active_request.start_paddr & m_data_block_mask; 156 assert(!active_request.write); 157 if (active_request.data != NULL) { 158 memcpy(&active_request.data[active_request.bytes_completed], 159 dblk.getData(offset, len), len); 160 } 161 issueNext(); 162} 163 164void 165DMASequencer::ackCallback() 166{ 167 issueNext(); 168} 169 170void 171DMASequencer::recordRequestType(DMASequencerRequestType requestType) 172{ 173 DPRINTF(RubyStats, "Recorded statistic: %s\n", 174 DMASequencerRequestType_to_string(requestType)); 175} 176 177DMASequencer * 178DMASequencerParams::create() 179{ 180 return new DMASequencer(this); 181} 182