DMASequencer.cc revision 11339
1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <memory> 30 31#include "debug/RubyDma.hh" 32#include "debug/RubyStats.hh" 33#include "mem/protocol/SequencerMsg.hh" 34#include "mem/protocol/SequencerRequestType.hh" 35#include "mem/ruby/system/DMASequencer.hh" 36#include "mem/ruby/system/RubySystem.hh" 37 38DMASequencer::DMASequencer(const Params *p) 39 : RubyPort(p) 40{ 41} 42 43void 44DMASequencer::init() 45{ 46 RubyPort::init(); 47 m_is_busy = false; 48 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); 49} 50 51RequestStatus 52DMASequencer::makeRequest(PacketPtr pkt) 53{ 54 if (m_is_busy) { 55 return RequestStatus_BufferFull; 56 } 57 58 Addr paddr = pkt->getAddr(); 59 uint8_t* data = pkt->getPtr<uint8_t>(); 60 int len = pkt->getSize(); 61 bool write = pkt->isWrite(); 62 63 assert(!m_is_busy); // only support one outstanding DMA request 64 m_is_busy = true; 65 66 active_request.start_paddr = paddr; 67 active_request.write = write; 68 active_request.data = data; 69 active_request.len = len; 70 active_request.bytes_completed = 0; 71 active_request.bytes_issued = 0; 72 active_request.pkt = pkt; 73 74 std::shared_ptr<SequencerMsg> msg = 75 std::make_shared<SequencerMsg>(clockEdge()); 76 msg->getPhysicalAddress() = paddr; 77 msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress()); 78 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; 79 int offset = paddr & m_data_block_mask; 80 81 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? 82 len : RubySystem::getBlockSizeBytes() - offset; 83 84 if (write && (data != NULL)) { 85 if (active_request.data != NULL) { 86 msg->getDataBlk().setData(data, offset, msg->getLen()); 87 } 88 } 89 90 assert(m_mandatory_q_ptr != NULL); 91 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); 92 active_request.bytes_issued += msg->getLen(); 93 94 return RequestStatus_Issued; 95} 96 97void 98DMASequencer::issueNext() 99{ 100 assert(m_is_busy); 101 active_request.bytes_completed = active_request.bytes_issued; 102 if (active_request.len == active_request.bytes_completed) { 103 // 104 // Must unset the busy flag before calling back the dma port because 105 // the callback may cause a previously nacked request to be reissued 106 // 107 DPRINTF(RubyDma, "DMA request completed\n"); 108 m_is_busy = false; 109 ruby_hit_callback(active_request.pkt); 110 return; 111 } 112 113 std::shared_ptr<SequencerMsg> msg = 114 std::make_shared<SequencerMsg>(clockEdge()); 115 msg->getPhysicalAddress() = active_request.start_paddr + 116 active_request.bytes_completed; 117 118 assert((msg->getPhysicalAddress() & m_data_block_mask) == 0); 119 msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress()); 120 121 msg->getType() = (active_request.write ? SequencerRequestType_ST : 122 SequencerRequestType_LD); 123 124 msg->getLen() = 125 (active_request.len - 126 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 127 active_request.len - active_request.bytes_completed : 128 RubySystem::getBlockSizeBytes()); 129 130 if (active_request.write) { 131 msg->getDataBlk(). 132 setData(&active_request.data[active_request.bytes_completed], 133 0, msg->getLen()); 134 } 135 136 assert(m_mandatory_q_ptr != NULL); 137 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); 138 active_request.bytes_issued += msg->getLen(); 139 DPRINTF(RubyDma, 140 "DMA request bytes issued %d, bytes completed %d, total len %d\n", 141 active_request.bytes_issued, active_request.bytes_completed, 142 active_request.len); 143} 144 145void 146DMASequencer::dataCallback(const DataBlock & dblk) 147{ 148 assert(m_is_busy); 149 int len = active_request.bytes_issued - active_request.bytes_completed; 150 int offset = 0; 151 if (active_request.bytes_completed == 0) 152 offset = active_request.start_paddr & m_data_block_mask; 153 assert(!active_request.write); 154 if (active_request.data != NULL) { 155 memcpy(&active_request.data[active_request.bytes_completed], 156 dblk.getData(offset, len), len); 157 } 158 issueNext(); 159} 160 161void 162DMASequencer::ackCallback() 163{ 164 issueNext(); 165} 166 167void 168DMASequencer::recordRequestType(DMASequencerRequestType requestType) 169{ 170 DPRINTF(RubyStats, "Recorded statistic: %s\n", 171 DMASequencerRequestType_to_string(requestType)); 172} 173 174DMASequencer * 175DMASequencerParams::create() 176{ 177 return new DMASequencer(this); 178} 179