DMASequencer.cc revision 10231
1/* 2 * Copyright (c) 2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "debug/RubyDma.hh" 30#include "debug/RubyStats.hh" 31#include "mem/protocol/SequencerMsg.hh" 32#include "mem/protocol/SequencerRequestType.hh" 33#include "mem/ruby/system/DMASequencer.hh" 34#include "mem/ruby/system/System.hh" 35 36DMASequencer::DMASequencer(const Params *p) 37 : RubyPort(p) 38{ 39} 40 41void 42DMASequencer::init() 43{ 44 RubyPort::init(); 45 m_is_busy = false; 46 m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); 47} 48 49RequestStatus 50DMASequencer::makeRequest(PacketPtr pkt) 51{ 52 if (m_is_busy) { 53 return RequestStatus_BufferFull; 54 } 55 56 uint64_t paddr = pkt->getAddr(); 57 uint8_t* data = pkt->getPtr<uint8_t>(true); 58 int len = pkt->getSize(); 59 bool write = pkt->isWrite(); 60 61 assert(!m_is_busy); // only support one outstanding DMA request 62 m_is_busy = true; 63 64 active_request.start_paddr = paddr; 65 active_request.write = write; 66 active_request.data = data; 67 active_request.len = len; 68 active_request.bytes_completed = 0; 69 active_request.bytes_issued = 0; 70 active_request.pkt = pkt; 71 72 SequencerMsg *msg = new SequencerMsg(clockEdge()); 73 msg->getPhysicalAddress() = Address(paddr); 74 msg->getLineAddress() = line_address(msg->getPhysicalAddress()); 75 msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; 76 int offset = paddr & m_data_block_mask; 77 78 msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? 79 len : RubySystem::getBlockSizeBytes() - offset; 80 81 if (write && (data != NULL)) { 82 if (active_request.data != NULL) { 83 msg->getDataBlk().setData(data, offset, msg->getLen()); 84 } 85 } 86 87 assert(m_mandatory_q_ptr != NULL); 88 m_mandatory_q_ptr->enqueue(msg); 89 active_request.bytes_issued += msg->getLen(); 90 91 return RequestStatus_Issued; 92} 93 94void 95DMASequencer::issueNext() 96{ 97 assert(m_is_busy); 98 active_request.bytes_completed = active_request.bytes_issued; 99 if (active_request.len == active_request.bytes_completed) { 100 // 101 // Must unset the busy flag before calling back the dma port because 102 // the callback may cause a previously nacked request to be reissued 103 // 104 DPRINTF(RubyDma, "DMA request completed\n"); 105 m_is_busy = false; 106 ruby_hit_callback(active_request.pkt); 107 return; 108 } 109 110 SequencerMsg *msg = new SequencerMsg(clockEdge()); 111 msg->getPhysicalAddress() = Address(active_request.start_paddr + 112 active_request.bytes_completed); 113 114 assert((msg->getPhysicalAddress().getAddress() & m_data_block_mask) == 0); 115 msg->getLineAddress() = line_address(msg->getPhysicalAddress()); 116 117 msg->getType() = (active_request.write ? SequencerRequestType_ST : 118 SequencerRequestType_LD); 119 120 msg->getLen() = 121 (active_request.len - 122 active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 123 active_request.len - active_request.bytes_completed : 124 RubySystem::getBlockSizeBytes()); 125 126 if (active_request.write) { 127 msg->getDataBlk(). 128 setData(&active_request.data[active_request.bytes_completed], 129 0, msg->getLen()); 130 msg->getType() = SequencerRequestType_ST; 131 } else { 132 msg->getType() = SequencerRequestType_LD; 133 } 134 135 assert(m_mandatory_q_ptr != NULL); 136 m_mandatory_q_ptr->enqueue(msg); 137 active_request.bytes_issued += msg->getLen(); 138 DPRINTF(RubyDma, 139 "DMA request bytes issued %d, bytes completed %d, total len %d\n", 140 active_request.bytes_issued, active_request.bytes_completed, 141 active_request.len); 142} 143 144void 145DMASequencer::dataCallback(const DataBlock & dblk) 146{ 147 assert(m_is_busy); 148 int len = active_request.bytes_issued - active_request.bytes_completed; 149 int offset = 0; 150 if (active_request.bytes_completed == 0) 151 offset = active_request.start_paddr & m_data_block_mask; 152 assert(!active_request.write); 153 if (active_request.data != NULL) { 154 memcpy(&active_request.data[active_request.bytes_completed], 155 dblk.getData(offset, len), len); 156 } 157 issueNext(); 158} 159 160void 161DMASequencer::ackCallback() 162{ 163 issueNext(); 164} 165 166void 167DMASequencer::recordRequestType(DMASequencerRequestType requestType) { 168 DPRINTF(RubyStats, "Recorded statistic: %s\n", 169 DMASequencerRequestType_to_string(requestType)); 170} 171 172DMASequencer * 173DMASequencerParams::create() 174{ 175 return new DMASequencer(this); 176} 177