DMASequencer.cc revision 11111
17008Snate@binkert.org/* 27008Snate@binkert.org * Copyright (c) 2008 Mark D. Hill and David A. Wood 37008Snate@binkert.org * All rights reserved. 47008Snate@binkert.org * 57008Snate@binkert.org * Redistribution and use in source and binary forms, with or without 67008Snate@binkert.org * modification, are permitted provided that the following conditions are 77008Snate@binkert.org * met: redistributions of source code must retain the above copyright 87008Snate@binkert.org * notice, this list of conditions and the following disclaimer; 97008Snate@binkert.org * redistributions in binary form must reproduce the above copyright 107008Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 117008Snate@binkert.org * documentation and/or other materials provided with the distribution; 127008Snate@binkert.org * neither the name of the copyright holders nor the names of its 137008Snate@binkert.org * contributors may be used to endorse or promote products derived from 147008Snate@binkert.org * this software without specific prior written permission. 157008Snate@binkert.org * 167008Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177008Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187008Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197008Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207008Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217008Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227008Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237008Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247008Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257008Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267008Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277008Snate@binkert.org */ 286285Snate@binkert.org 2910472Sandreas.hansson@arm.com#include <memory> 3010472Sandreas.hansson@arm.com 3110518Snilay@cs.wisc.edu#include "debug/Config.hh" 3210518Snilay@cs.wisc.edu#include "debug/Drain.hh" 338232Snate@binkert.org#include "debug/RubyDma.hh" 349104Shestness@cs.utexas.edu#include "debug/RubyStats.hh" 357039Snate@binkert.org#include "mem/protocol/SequencerMsg.hh" 367039Snate@binkert.org#include "mem/ruby/system/DMASequencer.hh" 3711108Sdavid.hashe@amd.com#include "mem/ruby/system/RubySystem.hh" 3810518Snilay@cs.wisc.edu#include "sim/system.hh" 396285Snate@binkert.org 406876Ssteve.reinhardt@amd.comDMASequencer::DMASequencer(const Params *p) 4110919Sbrandon.potter@amd.com : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version), 4210919Sbrandon.potter@amd.com m_controller(NULL), m_mandatory_q_ptr(NULL), 4310919Sbrandon.potter@amd.com m_usingRubyTester(p->using_ruby_tester), 4410706Spower.jg@gmail.com slave_port(csprintf("%s.slave", name()), this, 0, p->ruby_system, 4510706Spower.jg@gmail.com p->ruby_system->getAccessBackingStore()), 4610913Sandreas.sandberg@arm.com system(p->system), retry(false) 476285Snate@binkert.org{ 4810518Snilay@cs.wisc.edu assert(m_version != -1); 496285Snate@binkert.org} 506285Snate@binkert.org 517039Snate@binkert.orgvoid 527039Snate@binkert.orgDMASequencer::init() 536285Snate@binkert.org{ 5410518Snilay@cs.wisc.edu MemObject::init(); 5510518Snilay@cs.wisc.edu assert(m_controller != NULL); 5610518Snilay@cs.wisc.edu m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 577039Snate@binkert.org m_is_busy = false; 587039Snate@binkert.org m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); 5910519Snilay@cs.wisc.edu 6010519Snilay@cs.wisc.edu slave_port.sendRangeChange(); 616285Snate@binkert.org} 626285Snate@binkert.org 6310518Snilay@cs.wisc.eduBaseSlavePort & 6410518Snilay@cs.wisc.eduDMASequencer::getSlavePort(const std::string &if_name, PortID idx) 6510518Snilay@cs.wisc.edu{ 6610518Snilay@cs.wisc.edu // used by the CPUs to connect the caches to the interconnect, and 6710518Snilay@cs.wisc.edu // for the x86 case also the interrupt master 6810518Snilay@cs.wisc.edu if (if_name != "slave") { 6910518Snilay@cs.wisc.edu // pass it along to our super class 7010518Snilay@cs.wisc.edu return MemObject::getSlavePort(if_name, idx); 7110518Snilay@cs.wisc.edu } else { 7210518Snilay@cs.wisc.edu return slave_port; 7310518Snilay@cs.wisc.edu } 7410518Snilay@cs.wisc.edu} 7510518Snilay@cs.wisc.edu 7610518Snilay@cs.wisc.eduDMASequencer::MemSlavePort::MemSlavePort(const std::string &_name, 7710706Spower.jg@gmail.com DMASequencer *_port, PortID id, RubySystem* _ruby_system, 7810706Spower.jg@gmail.com bool _access_backing_store) 7910706Spower.jg@gmail.com : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 8010919Sbrandon.potter@amd.com m_ruby_system(_ruby_system), access_backing_store(_access_backing_store) 8110518Snilay@cs.wisc.edu{ 8210518Snilay@cs.wisc.edu DPRINTF(RubyDma, "Created slave memport on ruby sequencer %s\n", _name); 8310518Snilay@cs.wisc.edu} 8410518Snilay@cs.wisc.edu 8510518Snilay@cs.wisc.edubool 8610518Snilay@cs.wisc.eduDMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt) 8710518Snilay@cs.wisc.edu{ 8810518Snilay@cs.wisc.edu DPRINTF(RubyDma, "Timing request for address %#x on port %d\n", 8910518Snilay@cs.wisc.edu pkt->getAddr(), id); 9010518Snilay@cs.wisc.edu DMASequencer *seq = static_cast<DMASequencer *>(&owner); 9110518Snilay@cs.wisc.edu 9210518Snilay@cs.wisc.edu if (pkt->memInhibitAsserted()) 9310518Snilay@cs.wisc.edu panic("DMASequencer should never see an inhibited request\n"); 9410518Snilay@cs.wisc.edu 9510518Snilay@cs.wisc.edu assert(isPhysMemAddress(pkt->getAddr())); 9611025Snilay@cs.wisc.edu assert(getOffset(pkt->getAddr()) + pkt->getSize() <= 9710518Snilay@cs.wisc.edu RubySystem::getBlockSizeBytes()); 9810518Snilay@cs.wisc.edu 9910518Snilay@cs.wisc.edu // Submit the ruby request 10010518Snilay@cs.wisc.edu RequestStatus requestStatus = seq->makeRequest(pkt); 10110518Snilay@cs.wisc.edu 10210518Snilay@cs.wisc.edu // If the request successfully issued then we should return true. 10310518Snilay@cs.wisc.edu // Otherwise, we need to tell the port to retry at a later point 10410518Snilay@cs.wisc.edu // and return false. 10510518Snilay@cs.wisc.edu if (requestStatus == RequestStatus_Issued) { 10610518Snilay@cs.wisc.edu DPRINTF(RubyDma, "Request %s 0x%x issued\n", pkt->cmdString(), 10710518Snilay@cs.wisc.edu pkt->getAddr()); 10810518Snilay@cs.wisc.edu return true; 10910518Snilay@cs.wisc.edu } 11010518Snilay@cs.wisc.edu 11110518Snilay@cs.wisc.edu // Unless one is using the ruby tester, record the stalled M5 port for 11210518Snilay@cs.wisc.edu // later retry when the sequencer becomes free. 11310518Snilay@cs.wisc.edu if (!seq->m_usingRubyTester) { 11410518Snilay@cs.wisc.edu seq->retry = true; 11510518Snilay@cs.wisc.edu } 11610518Snilay@cs.wisc.edu 11710518Snilay@cs.wisc.edu DPRINTF(RubyDma, "Request for address %#x did not issued because %s\n", 11810518Snilay@cs.wisc.edu pkt->getAddr(), RequestStatus_to_string(requestStatus)); 11910518Snilay@cs.wisc.edu 12010518Snilay@cs.wisc.edu return false; 12110518Snilay@cs.wisc.edu} 12210518Snilay@cs.wisc.edu 12310518Snilay@cs.wisc.eduvoid 12410518Snilay@cs.wisc.eduDMASequencer::ruby_hit_callback(PacketPtr pkt) 12510518Snilay@cs.wisc.edu{ 12610518Snilay@cs.wisc.edu DPRINTF(RubyDma, "Hit callback for %s 0x%x\n", pkt->cmdString(), 12710518Snilay@cs.wisc.edu pkt->getAddr()); 12810518Snilay@cs.wisc.edu 12910518Snilay@cs.wisc.edu // The packet was destined for memory and has not yet been turned 13010518Snilay@cs.wisc.edu // into a response 13110518Snilay@cs.wisc.edu assert(system->isMemAddr(pkt->getAddr())); 13210518Snilay@cs.wisc.edu assert(pkt->isRequest()); 13310518Snilay@cs.wisc.edu slave_port.hitCallback(pkt); 13410518Snilay@cs.wisc.edu 13510518Snilay@cs.wisc.edu // If we had to stall the slave ports, wake it up because 13610518Snilay@cs.wisc.edu // the sequencer likely has free resources now. 13710518Snilay@cs.wisc.edu if (retry) { 13810518Snilay@cs.wisc.edu retry = false; 13910518Snilay@cs.wisc.edu DPRINTF(RubyDma,"Sequencer may now be free. SendRetry to port %s\n", 14010518Snilay@cs.wisc.edu slave_port.name()); 14110713Sandreas.hansson@arm.com slave_port.sendRetryReq(); 14210518Snilay@cs.wisc.edu } 14310518Snilay@cs.wisc.edu 14410518Snilay@cs.wisc.edu testDrainComplete(); 14510518Snilay@cs.wisc.edu} 14610518Snilay@cs.wisc.edu 14710518Snilay@cs.wisc.eduvoid 14810518Snilay@cs.wisc.eduDMASequencer::testDrainComplete() 14910518Snilay@cs.wisc.edu{ 15010518Snilay@cs.wisc.edu //If we weren't able to drain before, we might be able to now. 15110913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining) { 15210518Snilay@cs.wisc.edu unsigned int drainCount = outstandingCount(); 15310518Snilay@cs.wisc.edu DPRINTF(Drain, "Drain count: %u\n", drainCount); 15410518Snilay@cs.wisc.edu if (drainCount == 0) { 15510518Snilay@cs.wisc.edu DPRINTF(Drain, "DMASequencer done draining, signaling drain done\n"); 15610913Sandreas.sandberg@arm.com signalDrainDone(); 15710518Snilay@cs.wisc.edu } 15810518Snilay@cs.wisc.edu } 15910518Snilay@cs.wisc.edu} 16010518Snilay@cs.wisc.edu 16110913Sandreas.sandberg@arm.comDrainState 16210913Sandreas.sandberg@arm.comDMASequencer::drain() 16310518Snilay@cs.wisc.edu{ 16410518Snilay@cs.wisc.edu if (isDeadlockEventScheduled()) { 16510518Snilay@cs.wisc.edu descheduleDeadlockEvent(); 16610518Snilay@cs.wisc.edu } 16710518Snilay@cs.wisc.edu 16810518Snilay@cs.wisc.edu // If the DMASequencer is not empty, then it needs to clear all outstanding 16910913Sandreas.sandberg@arm.com // requests before it should call signalDrainDone() 17010518Snilay@cs.wisc.edu DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 17110518Snilay@cs.wisc.edu 17210518Snilay@cs.wisc.edu // Set status 17310913Sandreas.sandberg@arm.com if (outstandingCount() > 0) { 17410518Snilay@cs.wisc.edu DPRINTF(Drain, "DMASequencer not drained\n"); 17510913Sandreas.sandberg@arm.com return DrainState::Draining; 17610913Sandreas.sandberg@arm.com } else { 17710913Sandreas.sandberg@arm.com return DrainState::Drained; 17810518Snilay@cs.wisc.edu } 17910518Snilay@cs.wisc.edu} 18010518Snilay@cs.wisc.edu 18110518Snilay@cs.wisc.eduvoid 18210518Snilay@cs.wisc.eduDMASequencer::MemSlavePort::hitCallback(PacketPtr pkt) 18310518Snilay@cs.wisc.edu{ 18410518Snilay@cs.wisc.edu bool needsResponse = pkt->needsResponse(); 18510518Snilay@cs.wisc.edu assert(!pkt->isLLSC()); 18610518Snilay@cs.wisc.edu assert(!pkt->isFlush()); 18710518Snilay@cs.wisc.edu 18810518Snilay@cs.wisc.edu DPRINTF(RubyDma, "Hit callback needs response %d\n", needsResponse); 18910518Snilay@cs.wisc.edu 19010518Snilay@cs.wisc.edu // turn packet around to go back to requester if response expected 19110706Spower.jg@gmail.com 19210706Spower.jg@gmail.com if (access_backing_store) { 19310919Sbrandon.potter@amd.com m_ruby_system->getPhysMem()->access(pkt); 19410706Spower.jg@gmail.com } else if (needsResponse) { 19510706Spower.jg@gmail.com pkt->makeResponse(); 19610706Spower.jg@gmail.com } 19710706Spower.jg@gmail.com 19810518Snilay@cs.wisc.edu if (needsResponse) { 19910518Snilay@cs.wisc.edu DPRINTF(RubyDma, "Sending packet back over port\n"); 20010518Snilay@cs.wisc.edu // send next cycle 20110919Sbrandon.potter@amd.com DMASequencer *seq = static_cast<DMASequencer *>(&owner); 20210919Sbrandon.potter@amd.com RubySystem *rs = seq->m_ruby_system; 20310919Sbrandon.potter@amd.com schedTimingResp(pkt, curTick() + rs->clockPeriod()); 20410518Snilay@cs.wisc.edu } else { 20510518Snilay@cs.wisc.edu delete pkt; 20610518Snilay@cs.wisc.edu } 20710519Snilay@cs.wisc.edu 20810518Snilay@cs.wisc.edu DPRINTF(RubyDma, "Hit callback done!\n"); 20910518Snilay@cs.wisc.edu} 21010518Snilay@cs.wisc.edu 21110518Snilay@cs.wisc.edubool 21210518Snilay@cs.wisc.eduDMASequencer::MemSlavePort::isPhysMemAddress(Addr addr) const 21310518Snilay@cs.wisc.edu{ 21410518Snilay@cs.wisc.edu DMASequencer *seq = static_cast<DMASequencer *>(&owner); 21510518Snilay@cs.wisc.edu return seq->system->isMemAddr(addr); 21610518Snilay@cs.wisc.edu} 21710518Snilay@cs.wisc.edu 2187039Snate@binkert.orgRequestStatus 2198615Snilay@cs.wisc.eduDMASequencer::makeRequest(PacketPtr pkt) 2206285Snate@binkert.org{ 2217544SBrad.Beckmann@amd.com if (m_is_busy) { 2227544SBrad.Beckmann@amd.com return RequestStatus_BufferFull; 2237544SBrad.Beckmann@amd.com } 2247544SBrad.Beckmann@amd.com 22511025Snilay@cs.wisc.edu Addr paddr = pkt->getAddr(); 22610562Sandreas.hansson@arm.com uint8_t* data = pkt->getPtr<uint8_t>(); 2278615Snilay@cs.wisc.edu int len = pkt->getSize(); 2288615Snilay@cs.wisc.edu bool write = pkt->isWrite(); 2296285Snate@binkert.org 2307039Snate@binkert.org assert(!m_is_busy); // only support one outstanding DMA request 2317039Snate@binkert.org m_is_busy = true; 2326285Snate@binkert.org 2337039Snate@binkert.org active_request.start_paddr = paddr; 2347039Snate@binkert.org active_request.write = write; 2357039Snate@binkert.org active_request.data = data; 2367039Snate@binkert.org active_request.len = len; 2377039Snate@binkert.org active_request.bytes_completed = 0; 2387039Snate@binkert.org active_request.bytes_issued = 0; 2398615Snilay@cs.wisc.edu active_request.pkt = pkt; 2406285Snate@binkert.org 24110472Sandreas.hansson@arm.com std::shared_ptr<SequencerMsg> msg = 24210472Sandreas.hansson@arm.com std::make_shared<SequencerMsg>(clockEdge()); 24311025Snilay@cs.wisc.edu msg->getPhysicalAddress() = paddr; 24411025Snilay@cs.wisc.edu msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress()); 2457453Snate@binkert.org msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD; 2467039Snate@binkert.org int offset = paddr & m_data_block_mask; 2476888SBrad.Beckmann@amd.com 2487453Snate@binkert.org msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ? 2497039Snate@binkert.org len : RubySystem::getBlockSizeBytes() - offset; 2506888SBrad.Beckmann@amd.com 2517915SBrad.Beckmann@amd.com if (write && (data != NULL)) { 2527915SBrad.Beckmann@amd.com if (active_request.data != NULL) { 2537915SBrad.Beckmann@amd.com msg->getDataBlk().setData(data, offset, msg->getLen()); 2547915SBrad.Beckmann@amd.com } 2557039Snate@binkert.org } 2566888SBrad.Beckmann@amd.com 2577039Snate@binkert.org assert(m_mandatory_q_ptr != NULL); 25811111Snilay@cs.wisc.edu m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); 2597453Snate@binkert.org active_request.bytes_issued += msg->getLen(); 2606285Snate@binkert.org 2617039Snate@binkert.org return RequestStatus_Issued; 2626285Snate@binkert.org} 2636285Snate@binkert.org 2647039Snate@binkert.orgvoid 2657039Snate@binkert.orgDMASequencer::issueNext() 2666285Snate@binkert.org{ 26710231Ssteve.reinhardt@amd.com assert(m_is_busy); 2687039Snate@binkert.org active_request.bytes_completed = active_request.bytes_issued; 2697039Snate@binkert.org if (active_request.len == active_request.bytes_completed) { 2708162SBrad.Beckmann@amd.com // 2718162SBrad.Beckmann@amd.com // Must unset the busy flag before calling back the dma port because 2728162SBrad.Beckmann@amd.com // the callback may cause a previously nacked request to be reissued 2738162SBrad.Beckmann@amd.com // 2748162SBrad.Beckmann@amd.com DPRINTF(RubyDma, "DMA request completed\n"); 2758162SBrad.Beckmann@amd.com m_is_busy = false; 2767039Snate@binkert.org ruby_hit_callback(active_request.pkt); 2777039Snate@binkert.org return; 2787039Snate@binkert.org } 2796285Snate@binkert.org 28010472Sandreas.hansson@arm.com std::shared_ptr<SequencerMsg> msg = 28110472Sandreas.hansson@arm.com std::make_shared<SequencerMsg>(clockEdge()); 28211025Snilay@cs.wisc.edu msg->getPhysicalAddress() = active_request.start_paddr + 28311025Snilay@cs.wisc.edu active_request.bytes_completed; 2846888SBrad.Beckmann@amd.com 28511025Snilay@cs.wisc.edu assert((msg->getPhysicalAddress() & m_data_block_mask) == 0); 28611025Snilay@cs.wisc.edu msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress()); 2876888SBrad.Beckmann@amd.com 2887453Snate@binkert.org msg->getType() = (active_request.write ? SequencerRequestType_ST : 2897039Snate@binkert.org SequencerRequestType_LD); 2906888SBrad.Beckmann@amd.com 2917453Snate@binkert.org msg->getLen() = 2927039Snate@binkert.org (active_request.len - 2937039Snate@binkert.org active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? 2947039Snate@binkert.org active_request.len - active_request.bytes_completed : 2957039Snate@binkert.org RubySystem::getBlockSizeBytes()); 2966888SBrad.Beckmann@amd.com 2977039Snate@binkert.org if (active_request.write) { 2987453Snate@binkert.org msg->getDataBlk(). 2997039Snate@binkert.org setData(&active_request.data[active_request.bytes_completed], 3007453Snate@binkert.org 0, msg->getLen()); 3017039Snate@binkert.org } 3026888SBrad.Beckmann@amd.com 3037039Snate@binkert.org assert(m_mandatory_q_ptr != NULL); 30411111Snilay@cs.wisc.edu m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); 3057453Snate@binkert.org active_request.bytes_issued += msg->getLen(); 30610917Sbrandon.potter@amd.com DPRINTF(RubyDma, 3078160SBrad.Beckmann@amd.com "DMA request bytes issued %d, bytes completed %d, total len %d\n", 3088160SBrad.Beckmann@amd.com active_request.bytes_issued, active_request.bytes_completed, 3098160SBrad.Beckmann@amd.com active_request.len); 3106285Snate@binkert.org} 3116285Snate@binkert.org 3127039Snate@binkert.orgvoid 3137039Snate@binkert.orgDMASequencer::dataCallback(const DataBlock & dblk) 3146285Snate@binkert.org{ 31510231Ssteve.reinhardt@amd.com assert(m_is_busy); 3167039Snate@binkert.org int len = active_request.bytes_issued - active_request.bytes_completed; 3177039Snate@binkert.org int offset = 0; 3187039Snate@binkert.org if (active_request.bytes_completed == 0) 3197039Snate@binkert.org offset = active_request.start_paddr & m_data_block_mask; 32010231Ssteve.reinhardt@amd.com assert(!active_request.write); 3217915SBrad.Beckmann@amd.com if (active_request.data != NULL) { 3227915SBrad.Beckmann@amd.com memcpy(&active_request.data[active_request.bytes_completed], 3237915SBrad.Beckmann@amd.com dblk.getData(offset, len), len); 3247915SBrad.Beckmann@amd.com } 3257039Snate@binkert.org issueNext(); 3266285Snate@binkert.org} 3276285Snate@binkert.org 3287039Snate@binkert.orgvoid 3297039Snate@binkert.orgDMASequencer::ackCallback() 3306285Snate@binkert.org{ 3317039Snate@binkert.org issueNext(); 3326285Snate@binkert.org} 3336285Snate@binkert.org 3347039Snate@binkert.orgvoid 33510518Snilay@cs.wisc.eduDMASequencer::recordRequestType(DMASequencerRequestType requestType) 33610518Snilay@cs.wisc.edu{ 3379104Shestness@cs.utexas.edu DPRINTF(RubyStats, "Recorded statistic: %s\n", 3389104Shestness@cs.utexas.edu DMASequencerRequestType_to_string(requestType)); 3399104Shestness@cs.utexas.edu} 3409104Shestness@cs.utexas.edu 3416876Ssteve.reinhardt@amd.comDMASequencer * 3426876Ssteve.reinhardt@amd.comDMASequencerParams::create() 3436876Ssteve.reinhardt@amd.com{ 3446876Ssteve.reinhardt@amd.com return new DMASequencer(this); 3456876Ssteve.reinhardt@amd.com} 346