RubyCache.py revision 13665
18439SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 28439SN/A# All rights reserved. 38439SN/A# 48439SN/A# Redistribution and use in source and binary forms, with or without 58439SN/A# modification, are permitted provided that the following conditions are 68439SN/A# met: redistributions of source code must retain the above copyright 78439SN/A# notice, this list of conditions and the following disclaimer; 88439SN/A# redistributions in binary form must reproduce the above copyright 98439SN/A# notice, this list of conditions and the following disclaimer in the 108439SN/A# documentation and/or other materials provided with the distribution; 118439SN/A# neither the name of the copyright holders nor the names of its 128439SN/A# contributors may be used to endorse or promote products derived from 138439SN/A# this software without specific prior written permission. 148439SN/A# 158439SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 168439SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 178439SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 188439SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 198439SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 208439SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 218439SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 228439SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 238439SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 248439SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 258439SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 268439SN/A# 278439SN/A# Authors: Steve Reinhardt 288439SN/A# Brad Beckmann 298439SN/A 308439SN/Afrom m5.params import * 3110919SN/Afrom m5.proxy import * 3213665Sandreas.sandberg@arm.comfrom m5.objects.PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy 338439SN/Afrom m5.SimObject import SimObject 348439SN/A 358439SN/Aclass RubyCache(SimObject): 368439SN/A type = 'RubyCache' 378439SN/A cxx_class = 'CacheMemory' 3810301SN/A cxx_header = "mem/ruby/structures/CacheMemory.hh" 398439SN/A size = Param.MemorySize("capacity in bytes"); 408439SN/A assoc = Param.Int(""); 4110970SN/A replacement_policy = Param.ReplacementPolicy(PseudoLRUReplacementPolicy(), 4210970SN/A "") 438439SN/A start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line"); 448653SN/A is_icache = Param.Bool(False, "is instruction only cache"); 4511308Santhony.gutierrez@amd.com block_size = Param.MemorySize("0B", "block size in bytes. 0 means default RubyBlockSize") 469105SN/A 479105SN/A dataArrayBanks = Param.Int(1, "Number of banks for the data array") 489105SN/A tagArrayBanks = Param.Int(1, "Number of banks for the tag array") 499184SN/A dataAccessLatency = Param.Cycles(1, "cycles for a data array access") 509184SN/A tagAccessLatency = Param.Cycles(1, "cycles for a tag array access") 519105SN/A resourceStalls = Param.Bool(False, "stall if there is a resource failure") 5210919SN/A ruby_system = Param.RubySystem(Parent.any, "") 53