RubyCache.py revision 10970
19341SAndreas.Sandberg@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc.
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139341SAndreas.Sandberg@arm.com# this software without specific prior written permission.
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169341SAndreas.Sandberg@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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279341SAndreas.Sandberg@arm.com# Authors: Steve Reinhardt
289341SAndreas.Sandberg@arm.com#          Brad Beckmann
299341SAndreas.Sandberg@arm.com
309341SAndreas.Sandberg@arm.comfrom m5.params import *
319341SAndreas.Sandberg@arm.comfrom m5.proxy import *
329341SAndreas.Sandberg@arm.comfrom PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy
339341SAndreas.Sandberg@arm.comfrom m5.SimObject import SimObject
349341SAndreas.Sandberg@arm.com
359341SAndreas.Sandberg@arm.comclass RubyCache(SimObject):
369341SAndreas.Sandberg@arm.com    type = 'RubyCache'
379341SAndreas.Sandberg@arm.com    cxx_class = 'CacheMemory'
389341SAndreas.Sandberg@arm.com    cxx_header = "mem/ruby/structures/CacheMemory.hh"
399341SAndreas.Sandberg@arm.com    size = Param.MemorySize("capacity in bytes");
409341SAndreas.Sandberg@arm.com    latency = Param.Cycles("");
419341SAndreas.Sandberg@arm.com    assoc = Param.Int("");
429341SAndreas.Sandberg@arm.com    replacement_policy = Param.ReplacementPolicy(PseudoLRUReplacementPolicy(),
439341SAndreas.Sandberg@arm.com                         "")
449341SAndreas.Sandberg@arm.com    start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line");
459341SAndreas.Sandberg@arm.com    is_icache = Param.Bool(False, "is instruction only cache");
469341SAndreas.Sandberg@arm.com
47    dataArrayBanks = Param.Int(1, "Number of banks for the data array")
48    tagArrayBanks = Param.Int(1, "Number of banks for the tag array")
49    dataAccessLatency = Param.Cycles(1, "cycles for a data array access")
50    tagAccessLatency = Param.Cycles(1, "cycles for a tag array access")
51    resourceStalls = Param.Bool(False, "stall if there is a resource failure")
52    ruby_system = Param.RubySystem(Parent.any, "")
53