PerfectCacheMemory.hh revision 6145
111986Sandreas.sandberg@arm.com
211986Sandreas.sandberg@arm.com/*
311986Sandreas.sandberg@arm.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
411986Sandreas.sandberg@arm.com * All rights reserved.
511986Sandreas.sandberg@arm.com *
611986Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without
711986Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are
811986Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright
911986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer;
1011986Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright
1112391Sjason@lowepower.com * notice, this list of conditions and the following disclaimer in the
1212391Sjason@lowepower.com * documentation and/or other materials provided with the distribution;
1312391Sjason@lowepower.com * neither the name of the copyright holders nor the names of its
1412391Sjason@lowepower.com * contributors may be used to endorse or promote products derived from
1511986Sandreas.sandberg@arm.com * this software without specific prior written permission.
1611986Sandreas.sandberg@arm.com *
1711986Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1812391Sjason@lowepower.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1912037Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
2012037Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2112037Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2212037Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2312037Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2412037Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2512037Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2612037Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2712037Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2812037Sandreas.sandberg@arm.com */
2912037Sandreas.sandberg@arm.com
3012037Sandreas.sandberg@arm.com/*
3112037Sandreas.sandberg@arm.com * PerfectCacheMemory.h
3212391Sjason@lowepower.com *
3312391Sjason@lowepower.com * Description:
3411986Sandreas.sandberg@arm.com *
3512391Sjason@lowepower.com * $Id$
3612391Sjason@lowepower.com *
3712391Sjason@lowepower.com */
3812391Sjason@lowepower.com
3912391Sjason@lowepower.com#ifndef PERFECTCACHEMEMORY_H
4012391Sjason@lowepower.com#define PERFECTCACHEMEMORY_H
4112391Sjason@lowepower.com
4212391Sjason@lowepower.com#include "Global.hh"
4312391Sjason@lowepower.com#include "Map.hh"
4412391Sjason@lowepower.com#include "AccessPermission.hh"
4512391Sjason@lowepower.com#include "RubyConfig.hh"
4611986Sandreas.sandberg@arm.com#include "Address.hh"
4712391Sjason@lowepower.com#include "interface.hh"
4812391Sjason@lowepower.com#include "AbstractChip.hh"
4912391Sjason@lowepower.com
5012391Sjason@lowepower.comtemplate<class ENTRY>
5112391Sjason@lowepower.comclass PerfectCacheLineState {
5212391Sjason@lowepower.compublic:
5312391Sjason@lowepower.com  PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
5412391Sjason@lowepower.com  AccessPermission m_permission;
5512391Sjason@lowepower.com  ENTRY m_entry;
5612391Sjason@lowepower.com};
5711986Sandreas.sandberg@arm.com
5811986Sandreas.sandberg@arm.comtemplate<class ENTRY>
5912391Sjason@lowepower.comclass PerfectCacheMemory {
6011986Sandreas.sandberg@arm.compublic:
6112391Sjason@lowepower.com
6211986Sandreas.sandberg@arm.com  // Constructors
6312391Sjason@lowepower.com  PerfectCacheMemory(AbstractChip* chip_ptr);
6411986Sandreas.sandberg@arm.com
6511986Sandreas.sandberg@arm.com  // Destructor
6611986Sandreas.sandberg@arm.com  //~PerfectCacheMemory();
6712391Sjason@lowepower.com
6812391Sjason@lowepower.com  // Public Methods
6912391Sjason@lowepower.com
7012391Sjason@lowepower.com  static void printConfig(ostream& out);
7112391Sjason@lowepower.com
7212391Sjason@lowepower.com  // perform a cache access and see if we hit or not.  Return true on
7312391Sjason@lowepower.com  // a hit.
7412391Sjason@lowepower.com  bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry);
7512391Sjason@lowepower.com
7612391Sjason@lowepower.com  // tests to see if an address is present in the cache
7711986Sandreas.sandberg@arm.com  bool isTagPresent(const Address& address) const;
7811986Sandreas.sandberg@arm.com
7912391Sjason@lowepower.com  // Returns true if there is:
8011986Sandreas.sandberg@arm.com  //   a) a tag match on this address or there is
8112391Sjason@lowepower.com  //   b) an Invalid line in the same cache "way"
8212391Sjason@lowepower.com  bool cacheAvail(const Address& address) const;
8312391Sjason@lowepower.com
8412391Sjason@lowepower.com  // find an Invalid entry and sets the tag appropriate for the address
8512391Sjason@lowepower.com  void allocate(const Address& address);
8612391Sjason@lowepower.com
8712391Sjason@lowepower.com  void deallocate(const Address& address);
8812391Sjason@lowepower.com
8912391Sjason@lowepower.com  // Returns with the physical address of the conflicting cache line
9012391Sjason@lowepower.com  Address cacheProbe(const Address& newAddress) const;
9112391Sjason@lowepower.com
9212391Sjason@lowepower.com  // looks an address up in the cache
9312037Sandreas.sandberg@arm.com  ENTRY& lookup(const Address& address);
9412391Sjason@lowepower.com  const ENTRY& lookup(const Address& address) const;
9512391Sjason@lowepower.com
9611986Sandreas.sandberg@arm.com  // Get/Set permission of cache block
9712391Sjason@lowepower.com  AccessPermission getPermission(const Address& address) const;
9812391Sjason@lowepower.com  void changePermission(const Address& address, AccessPermission new_perm);
9912391Sjason@lowepower.com
10012391Sjason@lowepower.com  // Print cache contents
10112391Sjason@lowepower.com  void print(ostream& out) const;
10212391Sjason@lowepower.comprivate:
10312391Sjason@lowepower.com  // Private Methods
10412391Sjason@lowepower.com
10512391Sjason@lowepower.com  // Private copy constructor and assignment operator
10612391Sjason@lowepower.com  PerfectCacheMemory(const PerfectCacheMemory& obj);
10711986Sandreas.sandberg@arm.com  PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
10811986Sandreas.sandberg@arm.com
10912391Sjason@lowepower.com  // Data Members (m_prefix)
11012391Sjason@lowepower.com  Map<Address, PerfectCacheLineState<ENTRY> > m_map;
11112391Sjason@lowepower.com  AbstractChip* m_chip_ptr;
11212391Sjason@lowepower.com};
11312391Sjason@lowepower.com
11412391Sjason@lowepower.com// Output operator declaration
11511986Sandreas.sandberg@arm.com//ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj);
11612391Sjason@lowepower.com
11712391Sjason@lowepower.com// ******************* Definitions *******************
11812391Sjason@lowepower.com
11912391Sjason@lowepower.com// Output operator definition
12012391Sjason@lowepower.comtemplate<class ENTRY>
12112391Sjason@lowepower.comextern inline
12212391Sjason@lowepower.comostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj)
12312391Sjason@lowepower.com{
12412391Sjason@lowepower.com  obj.print(out);
12511986Sandreas.sandberg@arm.com  out << flush;
12611986Sandreas.sandberg@arm.com  return out;
12712391Sjason@lowepower.com}
12812391Sjason@lowepower.com
12912391Sjason@lowepower.com
13012391Sjason@lowepower.com// ****************************************************************
13112391Sjason@lowepower.com
13212391Sjason@lowepower.comtemplate<class ENTRY>
13311986Sandreas.sandberg@arm.comextern inline
13412391Sjason@lowepower.comPerfectCacheMemory<ENTRY>::PerfectCacheMemory(AbstractChip* chip_ptr)
13512391Sjason@lowepower.com{
13612391Sjason@lowepower.com  m_chip_ptr = chip_ptr;
13712391Sjason@lowepower.com}
13812391Sjason@lowepower.com
13912391Sjason@lowepower.com// STATIC METHODS
14012391Sjason@lowepower.com
14112391Sjason@lowepower.comtemplate<class ENTRY>
14212391Sjason@lowepower.comextern inline
14312391Sjason@lowepower.comvoid PerfectCacheMemory<ENTRY>::printConfig(ostream& out)
14412391Sjason@lowepower.com{
14512391Sjason@lowepower.com}
14612391Sjason@lowepower.com
14712391Sjason@lowepower.com// PUBLIC METHODS
14812391Sjason@lowepower.com
14912391Sjason@lowepower.comtemplate<class ENTRY>
15012391Sjason@lowepower.comextern inline
15112391Sjason@lowepower.combool PerfectCacheMemory<ENTRY>::tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry)
15212391Sjason@lowepower.com{
15312391Sjason@lowepower.com  ERROR_MSG("not implemented");
15411986Sandreas.sandberg@arm.com}
15511986Sandreas.sandberg@arm.com
15611986Sandreas.sandberg@arm.com// tests to see if an address is present in the cache
15711986Sandreas.sandberg@arm.comtemplate<class ENTRY>
15812391Sjason@lowepower.comextern inline
15912391Sjason@lowepower.combool PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const
16012391Sjason@lowepower.com{
16112391Sjason@lowepower.com  return m_map.exist(line_address(address));
16212391Sjason@lowepower.com}
16312391Sjason@lowepower.com
16412391Sjason@lowepower.comtemplate<class ENTRY>
16512391Sjason@lowepower.comextern inline
16612391Sjason@lowepower.combool PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
16712391Sjason@lowepower.com{
16811986Sandreas.sandberg@arm.com  return true;
16912391Sjason@lowepower.com}
17012391Sjason@lowepower.com
17112391Sjason@lowepower.com// find an Invalid or already allocated entry and sets the tag
17212391Sjason@lowepower.com// appropriate for the address
17312391Sjason@lowepower.comtemplate<class ENTRY>
17412391Sjason@lowepower.comextern inline
17512391Sjason@lowepower.comvoid PerfectCacheMemory<ENTRY>::allocate(const Address& address)
17612391Sjason@lowepower.com{
17711986Sandreas.sandberg@arm.com  PerfectCacheLineState<ENTRY> line_state;
17812391Sjason@lowepower.com  line_state.m_permission = AccessPermission_Busy;
17912391Sjason@lowepower.com  line_state.m_entry = ENTRY();
18011986Sandreas.sandberg@arm.com  m_map.add(line_address(address), line_state);
18111986Sandreas.sandberg@arm.com}
18211986Sandreas.sandberg@arm.com
18311986Sandreas.sandberg@arm.com// deallocate entry
18411986Sandreas.sandberg@arm.comtemplate<class ENTRY>
18511986Sandreas.sandberg@arm.comextern inline
18611986Sandreas.sandberg@arm.comvoid PerfectCacheMemory<ENTRY>::deallocate(const Address& address)
18711986Sandreas.sandberg@arm.com{
18811986Sandreas.sandberg@arm.com  m_map.erase(line_address(address));
18911986Sandreas.sandberg@arm.com}
19011986Sandreas.sandberg@arm.com
19111986Sandreas.sandberg@arm.com// Returns with the physical address of the conflicting cache line
19211986Sandreas.sandberg@arm.comtemplate<class ENTRY>
19311986Sandreas.sandberg@arm.comextern inline
19412391Sjason@lowepower.comAddress PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
19512391Sjason@lowepower.com{
19612391Sjason@lowepower.com  ERROR_MSG("cacheProbe called in perfect cache");
19712391Sjason@lowepower.com}
19812391Sjason@lowepower.com
19912391Sjason@lowepower.com// looks an address up in the cache
20012391Sjason@lowepower.comtemplate<class ENTRY>
20112391Sjason@lowepower.comextern inline
20212391Sjason@lowepower.comENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address)
20312391Sjason@lowepower.com{
20412391Sjason@lowepower.com  return m_map.lookup(line_address(address)).m_entry;
20512391Sjason@lowepower.com}
20611986Sandreas.sandberg@arm.com
20711986Sandreas.sandberg@arm.com// looks an address up in the cache
20811986Sandreas.sandberg@arm.comtemplate<class ENTRY>
20911986Sandreas.sandberg@arm.comextern inline
21011986Sandreas.sandberg@arm.comconst ENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address) const
21111986Sandreas.sandberg@arm.com{
21211986Sandreas.sandberg@arm.com  return m_map.lookup(line_address(address)).m_entry;
21311986Sandreas.sandberg@arm.com}
21411986Sandreas.sandberg@arm.com
21511986Sandreas.sandberg@arm.comtemplate<class ENTRY>
21611986Sandreas.sandberg@arm.comextern inline
21711986Sandreas.sandberg@arm.comAccessPermission PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const
21811986Sandreas.sandberg@arm.com{
21912037Sandreas.sandberg@arm.com  return m_map.lookup(line_address(address)).m_permission;
22012391Sjason@lowepower.com}
22112391Sjason@lowepower.com
22212391Sjason@lowepower.comtemplate<class ENTRY>
22312391Sjason@lowepower.comextern inline
22412391Sjason@lowepower.comvoid PerfectCacheMemory<ENTRY>::changePermission(const Address& address, AccessPermission new_perm)
22512391Sjason@lowepower.com{
22612391Sjason@lowepower.com  Address line_address = address;
22712391Sjason@lowepower.com  line_address.makeLineAddress();
22812391Sjason@lowepower.com  PerfectCacheLineState<ENTRY>& line_state = m_map.lookup(line_address);
22912391Sjason@lowepower.com  AccessPermission old_perm = line_state.m_permission;
23012037Sandreas.sandberg@arm.com  line_state.m_permission = new_perm;
23112037Sandreas.sandberg@arm.com}
23212037Sandreas.sandberg@arm.com
23312037Sandreas.sandberg@arm.comtemplate<class ENTRY>
23412391Sjason@lowepower.comextern inline
23512391Sjason@lowepower.comvoid PerfectCacheMemory<ENTRY>::print(ostream& out) const
23612037Sandreas.sandberg@arm.com{
23712391Sjason@lowepower.com}
23812037Sandreas.sandberg@arm.com
23912037Sandreas.sandberg@arm.com#endif //PERFECTCACHEMEMORY_H
24012037Sandreas.sandberg@arm.com