PerfectCacheMemory.hh revision 7806
110037SARM gem5 Developers/* 210037SARM gem5 Developers * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 310037SARM gem5 Developers * All rights reserved. 410037SARM gem5 Developers * 510037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 610037SARM gem5 Developers * modification, are permitted provided that the following conditions are 710037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 810037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 910037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1010037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 1110037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 1210037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 1310037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 1410037SARM gem5 Developers * this software without specific prior written permission. 1510037SARM gem5 Developers * 1610037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710037SARM gem5 Developers */ 2810037SARM gem5 Developers 2910037SARM gem5 Developers#ifndef __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__ 3010037SARM gem5 Developers#define __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__ 3110037SARM gem5 Developers 3210037SARM gem5 Developers#include "base/hashmap.hh" 3310037SARM gem5 Developers#include "mem/protocol/AccessPermission.hh" 3410037SARM gem5 Developers#include "mem/ruby/common/Address.hh" 3510037SARM gem5 Developers#include "mem/ruby/common/Global.hh" 3610037SARM gem5 Developers 3710037SARM gem5 Developerstemplate<class ENTRY> 3810037SARM gem5 Developersstruct PerfectCacheLineState 3910037SARM gem5 Developers{ 4010037SARM gem5 Developers PerfectCacheLineState() { m_permission = AccessPermission_NUM; } 4110037SARM gem5 Developers AccessPermission m_permission; 4210037SARM gem5 Developers ENTRY m_entry; 4310037SARM gem5 Developers}; 4410037SARM gem5 Developers 4510037SARM gem5 Developerstemplate<class ENTRY> 4610037SARM gem5 Developersinline std::ostream& 4710037SARM gem5 Developersoperator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj) 4810037SARM gem5 Developers{ 4910037SARM gem5 Developers return out; 5010037SARM gem5 Developers} 5110037SARM gem5 Developers 5210037SARM gem5 Developerstemplate<class ENTRY> 5310037SARM gem5 Developersclass PerfectCacheMemory 5410037SARM gem5 Developers{ 5510037SARM gem5 Developers public: 5610037SARM gem5 Developers PerfectCacheMemory(); 5710037SARM gem5 Developers 5810037SARM gem5 Developers static void printConfig(std::ostream& out); 5910037SARM gem5 Developers 6010037SARM gem5 Developers // perform a cache access and see if we hit or not. Return true 6110037SARM gem5 Developers // on a hit. 6210037SARM gem5 Developers bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry); 6310037SARM gem5 Developers 6410037SARM gem5 Developers // tests to see if an address is present in the cache 6510037SARM gem5 Developers bool isTagPresent(const Address& address) const; 6610037SARM gem5 Developers 6710037SARM gem5 Developers // Returns true if there is: 6810037SARM gem5 Developers // a) a tag match on this address or there is 6910037SARM gem5 Developers // b) an Invalid line in the same cache "way" 7010037SARM gem5 Developers bool cacheAvail(const Address& address) const; 7110037SARM gem5 Developers 7210037SARM gem5 Developers // find an Invalid entry and sets the tag appropriate for the address 7310037SARM gem5 Developers void allocate(const Address& address); 7410037SARM gem5 Developers 7510037SARM gem5 Developers void deallocate(const Address& address); 7610037SARM gem5 Developers 7710037SARM gem5 Developers // Returns with the physical address of the conflicting cache line 7810037SARM gem5 Developers Address cacheProbe(const Address& newAddress) const; 7910037SARM gem5 Developers 8010037SARM gem5 Developers // looks an address up in the cache 8110037SARM gem5 Developers ENTRY& lookup(const Address& address); 8210037SARM gem5 Developers const ENTRY& lookup(const Address& address) const; 8310037SARM gem5 Developers 8410037SARM gem5 Developers // Get/Set permission of cache block 8510037SARM gem5 Developers AccessPermission getPermission(const Address& address) const; 8610037SARM gem5 Developers void changePermission(const Address& address, AccessPermission new_perm); 8710037SARM gem5 Developers 8810037SARM gem5 Developers // Print cache contents 8910037SARM gem5 Developers void print(std::ostream& out) const; 9010037SARM gem5 Developers 9110037SARM gem5 Developers private: 9210037SARM gem5 Developers // Private copy constructor and assignment operator 9310037SARM gem5 Developers PerfectCacheMemory(const PerfectCacheMemory& obj); 9410037SARM gem5 Developers PerfectCacheMemory& operator=(const PerfectCacheMemory& obj); 9510037SARM gem5 Developers 9610037SARM gem5 Developers // Data Members (m_prefix) 9710037SARM gem5 Developers m5::hash_map<Address, PerfectCacheLineState<ENTRY> > m_map; 9810037SARM gem5 Developers}; 9910037SARM gem5 Developers 10010037SARM gem5 Developerstemplate<class ENTRY> 10110037SARM gem5 Developersinline std::ostream& 10210037SARM gem5 Developersoperator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj) 10310037SARM gem5 Developers{ 10410037SARM gem5 Developers obj.print(out); 10510037SARM gem5 Developers out << std::flush; 10610037SARM gem5 Developers return out; 10710037SARM gem5 Developers} 10810037SARM gem5 Developers 10910037SARM gem5 Developerstemplate<class ENTRY> 11010037SARM gem5 Developersinline 11110037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::PerfectCacheMemory() 11210037SARM gem5 Developers{ 11310037SARM gem5 Developers} 11410037SARM gem5 Developers 11510037SARM gem5 Developerstemplate<class ENTRY> 11610037SARM gem5 Developersinline void 11710037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::printConfig(std::ostream& out) 11810037SARM gem5 Developers{ 11910037SARM gem5 Developers} 12010037SARM gem5 Developers 12110037SARM gem5 Developerstemplate<class ENTRY> 12210037SARM gem5 Developersinline bool 12310037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::tryCacheAccess(const CacheMsg& msg, 12410037SARM gem5 Developers bool& block_stc, ENTRY*& entry) 12510037SARM gem5 Developers{ 12610037SARM gem5 Developers panic("not implemented"); 12710037SARM gem5 Developers return true; 12810037SARM gem5 Developers} 12910037SARM gem5 Developers 13010037SARM gem5 Developers// tests to see if an address is present in the cache 13110037SARM gem5 Developerstemplate<class ENTRY> 13210037SARM gem5 Developersinline bool 13310037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const 13410037SARM gem5 Developers{ 13510037SARM gem5 Developers return m_map.count(line_address(address)) > 0; 13610037SARM gem5 Developers} 13710037SARM gem5 Developers 13810037SARM gem5 Developerstemplate<class ENTRY> 13910037SARM gem5 Developersinline bool 14010037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const 14110037SARM gem5 Developers{ 14210037SARM gem5 Developers return true; 14310037SARM gem5 Developers} 14410037SARM gem5 Developers 14510037SARM gem5 Developers// find an Invalid or already allocated entry and sets the tag 14610037SARM gem5 Developers// appropriate for the address 14710037SARM gem5 Developerstemplate<class ENTRY> 14810037SARM gem5 Developersinline void 14910037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::allocate(const Address& address) 15010037SARM gem5 Developers{ 15110037SARM gem5 Developers PerfectCacheLineState<ENTRY> line_state; 15210037SARM gem5 Developers line_state.m_permission = AccessPermission_Busy; 15310037SARM gem5 Developers line_state.m_entry = ENTRY(); 15410037SARM gem5 Developers m_map[line_address(address)] = line_state; 15510037SARM gem5 Developers} 15610037SARM gem5 Developers 15710037SARM gem5 Developers// deallocate entry 15810037SARM gem5 Developerstemplate<class ENTRY> 15910037SARM gem5 Developersinline void 16010037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::deallocate(const Address& address) 16110037SARM gem5 Developers{ 16210037SARM gem5 Developers m_map.erase(line_address(address)); 16310037SARM gem5 Developers} 16410037SARM gem5 Developers 16510037SARM gem5 Developers// Returns with the physical address of the conflicting cache line 16610037SARM gem5 Developerstemplate<class ENTRY> 16710037SARM gem5 Developersinline Address 16810037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const 16910037SARM gem5 Developers{ 17010037SARM gem5 Developers panic("cacheProbe called in perfect cache"); 17110037SARM gem5 Developers return newAddress; 17210037SARM gem5 Developers} 17310037SARM gem5 Developers 17410037SARM gem5 Developers// looks an address up in the cache 17510037SARM gem5 Developerstemplate<class ENTRY> 17610037SARM gem5 Developersinline ENTRY& 17710037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::lookup(const Address& address) 17810037SARM gem5 Developers{ 17910037SARM gem5 Developers return m_map[line_address(address)].m_entry; 18010037SARM gem5 Developers} 18110037SARM gem5 Developers 18210037SARM gem5 Developers// looks an address up in the cache 18310037SARM gem5 Developerstemplate<class ENTRY> 18410037SARM gem5 Developersinline const ENTRY& 18510037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::lookup(const Address& address) const 18610037SARM gem5 Developers{ 18710037SARM gem5 Developers return m_map[line_address(address)].m_entry; 18810037SARM gem5 Developers} 18910037SARM gem5 Developers 19010037SARM gem5 Developerstemplate<class ENTRY> 19110037SARM gem5 Developersinline AccessPermission 19210037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::getPermission(const Address& address) const 19310037SARM gem5 Developers{ 19410037SARM gem5 Developers return m_map[line_address(address)].m_permission; 19510037SARM gem5 Developers} 19610037SARM gem5 Developers 19710037SARM gem5 Developerstemplate<class ENTRY> 19810037SARM gem5 Developersinline void 19910037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::changePermission(const Address& address, 20010037SARM gem5 Developers AccessPermission new_perm) 20110037SARM gem5 Developers{ 20210037SARM gem5 Developers Address line_address = address; 20310037SARM gem5 Developers line_address.makeLineAddress(); 20410037SARM gem5 Developers PerfectCacheLineState<ENTRY>& line_state = m_map[line_address]; 20510037SARM gem5 Developers AccessPermission old_perm = line_state.m_permission; 20610037SARM gem5 Developers line_state.m_permission = new_perm; 20710037SARM gem5 Developers} 20810037SARM gem5 Developers 20910037SARM gem5 Developerstemplate<class ENTRY> 21010037SARM gem5 Developersinline void 21110037SARM gem5 DevelopersPerfectCacheMemory<ENTRY>::print(std::ostream& out) const 21210037SARM gem5 Developers{ 21310037SARM gem5 Developers} 21410037SARM gem5 Developers 21510037SARM gem5 Developers#endif // __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__ 21610037SARM gem5 Developers