PerfectCacheMemory.hh revision 7039 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__
30#define __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__
31
32#include "mem/gems_common/Map.hh"
33#include "mem/protocol/AccessPermission.hh"
34#include "mem/ruby/common/Address.hh"
35#include "mem/ruby/common/Global.hh"
36
37template<class ENTRY>
38struct PerfectCacheLineState
39{
40    PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
41    AccessPermission m_permission;
42    ENTRY m_entry;
43};
44
45template<class ENTRY>
46inline ostream&
47operator<<(ostream& out, const PerfectCacheLineState<ENTRY>& obj)
48{
49    return out;
50}
51
52template<class ENTRY>
53class PerfectCacheMemory
54{
55  public:
56    PerfectCacheMemory();
57
58    static void printConfig(ostream& out);
59
60    // perform a cache access and see if we hit or not.  Return true
61    // on a hit.
62    bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry);
63
64    // tests to see if an address is present in the cache
65    bool isTagPresent(const Address& address) const;
66
67    // Returns true if there is:
68    //   a) a tag match on this address or there is
69    //   b) an Invalid line in the same cache "way"
70    bool cacheAvail(const Address& address) const;
71
72    // find an Invalid entry and sets the tag appropriate for the address
73    void allocate(const Address& address);
74
75    void deallocate(const Address& address);
76
77    // Returns with the physical address of the conflicting cache line
78    Address cacheProbe(const Address& newAddress) const;
79
80    // looks an address up in the cache
81    ENTRY& lookup(const Address& address);
82    const ENTRY& lookup(const Address& address) const;
83
84    // Get/Set permission of cache block
85    AccessPermission getPermission(const Address& address) const;
86    void changePermission(const Address& address, AccessPermission new_perm);
87
88    // Print cache contents
89    void print(ostream& out) const;
90
91  private:
92    // Private copy constructor and assignment operator
93    PerfectCacheMemory(const PerfectCacheMemory& obj);
94    PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
95
96    // Data Members (m_prefix)
97    Map<Address, PerfectCacheLineState<ENTRY> > m_map;
98};
99
100template<class ENTRY>
101inline ostream&
102operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj)
103{
104    obj.print(out);
105    out << flush;
106    return out;
107}
108
109template<class ENTRY>
110inline
111PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
112{
113}
114
115template<class ENTRY>
116inline void
117PerfectCacheMemory<ENTRY>::printConfig(ostream& out)
118{
119}
120
121template<class ENTRY>
122inline bool
123PerfectCacheMemory<ENTRY>::tryCacheAccess(const CacheMsg& msg,
124                                          bool& block_stc, ENTRY*& entry)
125{
126    ERROR_MSG("not implemented");
127}
128
129// tests to see if an address is present in the cache
130template<class ENTRY>
131inline bool
132PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const
133{
134    return m_map.exist(line_address(address));
135}
136
137template<class ENTRY>
138inline bool
139PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
140{
141    return true;
142}
143
144// find an Invalid or already allocated entry and sets the tag
145// appropriate for the address
146template<class ENTRY>
147inline void
148PerfectCacheMemory<ENTRY>::allocate(const Address& address)
149{
150    PerfectCacheLineState<ENTRY> line_state;
151    line_state.m_permission = AccessPermission_Busy;
152    line_state.m_entry = ENTRY();
153    m_map.add(line_address(address), line_state);
154}
155
156// deallocate entry
157template<class ENTRY>
158inline void
159PerfectCacheMemory<ENTRY>::deallocate(const Address& address)
160{
161    m_map.erase(line_address(address));
162}
163
164// Returns with the physical address of the conflicting cache line
165template<class ENTRY>
166inline Address
167PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
168{
169    ERROR_MSG("cacheProbe called in perfect cache");
170}
171
172// looks an address up in the cache
173template<class ENTRY>
174inline ENTRY&
175PerfectCacheMemory<ENTRY>::lookup(const Address& address)
176{
177    return m_map.lookup(line_address(address)).m_entry;
178}
179
180// looks an address up in the cache
181template<class ENTRY>
182inline const ENTRY&
183PerfectCacheMemory<ENTRY>::lookup(const Address& address) const
184{
185    return m_map.lookup(line_address(address)).m_entry;
186}
187
188template<class ENTRY>
189inline AccessPermission
190PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const
191{
192    return m_map.lookup(line_address(address)).m_permission;
193}
194
195template<class ENTRY>
196inline void
197PerfectCacheMemory<ENTRY>::changePermission(const Address& address,
198                                            AccessPermission new_perm)
199{
200    Address line_address = address;
201    line_address.makeLineAddress();
202    PerfectCacheLineState<ENTRY>& line_state = m_map.lookup(line_address);
203    AccessPermission old_perm = line_state.m_permission;
204    line_state.m_permission = new_perm;
205}
206
207template<class ENTRY>
208inline void
209PerfectCacheMemory<ENTRY>::print(ostream& out) const
210{
211}
212
213#endif // __MEM_RUBY_SYSTEM_PERFECTCACHEMEMORY_HH__
214