PerfectCacheMemory.hh revision 6154 
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * PerfectCacheMemory.h
32 *
33 * Description:
34 *
35 * $Id$
36 *
37 */
38
39#ifndef PERFECTCACHEMEMORY_H
40#define PERFECTCACHEMEMORY_H
41
42#include "mem/ruby/common/Global.hh"
43#include "mem/gems_common/Map.hh"
44#include "mem/protocol/AccessPermission.hh"
45#include "mem/ruby/config/RubyConfig.hh"
46#include "mem/ruby/common/Address.hh"
47#include "mem/ruby/slicc_interface/AbstractChip.hh"
48
49template<class ENTRY>
50class PerfectCacheLineState {
51public:
52  PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
53  AccessPermission m_permission;
54  ENTRY m_entry;
55};
56
57template<class ENTRY>
58class PerfectCacheMemory {
59public:
60
61  // Constructors
62  PerfectCacheMemory(AbstractChip* chip_ptr);
63
64  // Destructor
65  //~PerfectCacheMemory();
66
67  // Public Methods
68
69  static void printConfig(ostream& out);
70
71  // perform a cache access and see if we hit or not.  Return true on
72  // a hit.
73  bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry);
74
75  // tests to see if an address is present in the cache
76  bool isTagPresent(const Address& address) const;
77
78  // Returns true if there is:
79  //   a) a tag match on this address or there is
80  //   b) an Invalid line in the same cache "way"
81  bool cacheAvail(const Address& address) const;
82
83  // find an Invalid entry and sets the tag appropriate for the address
84  void allocate(const Address& address);
85
86  void deallocate(const Address& address);
87
88  // Returns with the physical address of the conflicting cache line
89  Address cacheProbe(const Address& newAddress) const;
90
91  // looks an address up in the cache
92  ENTRY& lookup(const Address& address);
93  const ENTRY& lookup(const Address& address) const;
94
95  // Get/Set permission of cache block
96  AccessPermission getPermission(const Address& address) const;
97  void changePermission(const Address& address, AccessPermission new_perm);
98
99  // Print cache contents
100  void print(ostream& out) const;
101private:
102  // Private Methods
103
104  // Private copy constructor and assignment operator
105  PerfectCacheMemory(const PerfectCacheMemory& obj);
106  PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
107
108  // Data Members (m_prefix)
109  Map<Address, PerfectCacheLineState<ENTRY> > m_map;
110  AbstractChip* m_chip_ptr;
111};
112
113// Output operator declaration
114//ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj);
115
116// ******************* Definitions *******************
117
118// Output operator definition
119template<class ENTRY>
120extern inline
121ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj)
122{
123  obj.print(out);
124  out << flush;
125  return out;
126}
127
128
129// ****************************************************************
130
131template<class ENTRY>
132extern inline
133PerfectCacheMemory<ENTRY>::PerfectCacheMemory(AbstractChip* chip_ptr)
134{
135  m_chip_ptr = chip_ptr;
136}
137
138// STATIC METHODS
139
140template<class ENTRY>
141extern inline
142void PerfectCacheMemory<ENTRY>::printConfig(ostream& out)
143{
144}
145
146// PUBLIC METHODS
147
148template<class ENTRY>
149extern inline
150bool PerfectCacheMemory<ENTRY>::tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry)
151{
152  ERROR_MSG("not implemented");
153}
154
155// tests to see if an address is present in the cache
156template<class ENTRY>
157extern inline
158bool PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const
159{
160  return m_map.exist(line_address(address));
161}
162
163template<class ENTRY>
164extern inline
165bool PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
166{
167  return true;
168}
169
170// find an Invalid or already allocated entry and sets the tag
171// appropriate for the address
172template<class ENTRY>
173extern inline
174void PerfectCacheMemory<ENTRY>::allocate(const Address& address)
175{
176  PerfectCacheLineState<ENTRY> line_state;
177  line_state.m_permission = AccessPermission_Busy;
178  line_state.m_entry = ENTRY();
179  m_map.add(line_address(address), line_state);
180}
181
182// deallocate entry
183template<class ENTRY>
184extern inline
185void PerfectCacheMemory<ENTRY>::deallocate(const Address& address)
186{
187  m_map.erase(line_address(address));
188}
189
190// Returns with the physical address of the conflicting cache line
191template<class ENTRY>
192extern inline
193Address PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
194{
195  ERROR_MSG("cacheProbe called in perfect cache");
196}
197
198// looks an address up in the cache
199template<class ENTRY>
200extern inline
201ENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address)
202{
203  return m_map.lookup(line_address(address)).m_entry;
204}
205
206// looks an address up in the cache
207template<class ENTRY>
208extern inline
209const ENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address) const
210{
211  return m_map.lookup(line_address(address)).m_entry;
212}
213
214template<class ENTRY>
215extern inline
216AccessPermission PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const
217{
218  return m_map.lookup(line_address(address)).m_permission;
219}
220
221template<class ENTRY>
222extern inline
223void PerfectCacheMemory<ENTRY>::changePermission(const Address& address, AccessPermission new_perm)
224{
225  Address line_address = address;
226  line_address.makeLineAddress();
227  PerfectCacheLineState<ENTRY>& line_state = m_map.lookup(line_address);
228  AccessPermission old_perm = line_state.m_permission;
229  line_state.m_permission = new_perm;
230}
231
232template<class ENTRY>
233extern inline
234void PerfectCacheMemory<ENTRY>::print(ostream& out) const
235{
236}
237
238#endif //PERFECTCACHEMEMORY_H
239