PerfectCacheMemory.hh revision 11025
16899SN/A/* 26899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36899SN/A * All rights reserved. 46899SN/A * 56899SN/A * Redistribution and use in source and binary forms, with or without 66899SN/A * modification, are permitted provided that the following conditions are 76899SN/A * met: redistributions of source code must retain the above copyright 86899SN/A * notice, this list of conditions and the following disclaimer; 96899SN/A * redistributions in binary form must reproduce the above copyright 106899SN/A * notice, this list of conditions and the following disclaimer in the 116899SN/A * documentation and/or other materials provided with the distribution; 126899SN/A * neither the name of the copyright holders nor the names of its 136899SN/A * contributors may be used to endorse or promote products derived from 146899SN/A * this software without specific prior written permission. 156899SN/A * 166899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276899SN/A */ 286899SN/A 296899SN/A#ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ 307056SN/A#define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ 317632SBrad.Beckmann@amd.com 327632SBrad.Beckmann@amd.com#include "base/hashmap.hh" 338232Snate@binkert.org#include "mem/protocol/AccessPermission.hh" 346899SN/A#include "mem/ruby/common/Address.hh" 358932SBrad.Beckmann@amd.com 368932SBrad.Beckmann@amd.comtemplate<class ENTRY> 378932SBrad.Beckmann@amd.comstruct PerfectCacheLineState 386899SN/A{ 397053SN/A PerfectCacheLineState() { m_permission = AccessPermission_NUM; } 407053SN/A AccessPermission m_permission; 416899SN/A ENTRY m_entry; 427053SN/A}; 437053SN/A 446899SN/Atemplate<class ENTRY> 457053SN/Ainline std::ostream& 467053SN/Aoperator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj) 477053SN/A{ 487053SN/A return out; 497053SN/A} 507053SN/A 517053SN/Atemplate<class ENTRY> 527053SN/Aclass PerfectCacheMemory 536899SN/A{ 547053SN/A public: 557053SN/A PerfectCacheMemory(); 567053SN/A 577053SN/A // tests to see if an address is present in the cache 587053SN/A bool isTagPresent(Addr address) const; 597053SN/A 607053SN/A // Returns true if there is: 617053SN/A // a) a tag match on this address or there is 627053SN/A // b) an Invalid line in the same cache "way" 636899SN/A bool cacheAvail(Addr address) const; 647053SN/A 657053SN/A // find an Invalid entry and sets the tag appropriate for the address 667053SN/A void allocate(Addr address); 677053SN/A 687053SN/A void deallocate(Addr address); 697053SN/A 707053SN/A // Returns with the physical address of the conflicting cache line 716899SN/A Addr cacheProbe(Addr newAddress) const; 726899SN/A 736899SN/A // looks an address up in the cache 746899SN/A ENTRY* lookup(Addr address); 757053SN/A const ENTRY* lookup(Addr address) const; 767053SN/A 777053SN/A // Get/Set permission of cache block 786899SN/A AccessPermission getPermission(Addr address) const; 796899SN/A void changePermission(Addr address, AccessPermission new_perm); 807053SN/A 817053SN/A // Print cache contents 826899SN/A void print(std::ostream& out) const; 837056SN/A 847053SN/A private: 857805Snilay@cs.wisc.edu // Private copy constructor and assignment operator 867053SN/A PerfectCacheMemory(const PerfectCacheMemory& obj); 876899SN/A PerfectCacheMemory& operator=(const PerfectCacheMemory& obj); 886899SN/A 897053SN/A // Data Members (m_prefix) 907455SN/A m5::hash_map<Addr, PerfectCacheLineState<ENTRY> > m_map; 917053SN/A}; 927053SN/A 937053SN/Atemplate<class ENTRY> 947053SN/Ainline std::ostream& 956899SN/Aoperator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj) 966899SN/A{ 977053SN/A obj.print(out); 988932SBrad.Beckmann@amd.com out << std::flush; 997053SN/A return out; 1007053SN/A} 1017455SN/A 1027053SN/Atemplate<class ENTRY> 1037454SN/Ainline 1046899SN/APerfectCacheMemory<ENTRY>::PerfectCacheMemory() 1056899SN/A{ 1067053SN/A} 1077053SN/A 1086899SN/A// tests to see if an address is present in the cache 1099108SBrad.Beckmann@amd.comtemplate<class ENTRY> 1107053SN/Ainline bool 1116899SN/APerfectCacheMemory<ENTRY>::isTagPresent(Addr address) const 1126899SN/A{ 1137053SN/A return m_map.count(makeLineAddress(address)) > 0; 1147053SN/A} 1156899SN/A 1167780Snilay@cs.wisc.edutemplate<class ENTRY> 1176899SN/Ainline bool 1187455SN/APerfectCacheMemory<ENTRY>::cacheAvail(Addr address) const 1197455SN/A{ 1207455SN/A return true; 1217053SN/A} 1227455SN/A 1237455SN/A// find an Invalid or already allocated entry and sets the tag 1247455SN/A// appropriate for the address 1257455SN/Atemplate<class ENTRY> 1266899SN/Ainline void 1276899SN/APerfectCacheMemory<ENTRY>::allocate(Addr address) 1287053SN/A{ 1297055SN/A PerfectCacheLineState<ENTRY> line_state; 1306899SN/A line_state.m_permission = AccessPermission_Invalid; 1316899SN/A line_state.m_entry = ENTRY(); 132 m_map[makeLineAddress(address)] = line_state; 133} 134 135// deallocate entry 136template<class ENTRY> 137inline void 138PerfectCacheMemory<ENTRY>::deallocate(Addr address) 139{ 140 m_map.erase(makeLineAddress(address)); 141} 142 143// Returns with the physical address of the conflicting cache line 144template<class ENTRY> 145inline Addr 146PerfectCacheMemory<ENTRY>::cacheProbe(Addr newAddress) const 147{ 148 panic("cacheProbe called in perfect cache"); 149 return newAddress; 150} 151 152// looks an address up in the cache 153template<class ENTRY> 154inline ENTRY* 155PerfectCacheMemory<ENTRY>::lookup(Addr address) 156{ 157 return &m_map[makeLineAddress(address)].m_entry; 158} 159 160// looks an address up in the cache 161template<class ENTRY> 162inline const ENTRY* 163PerfectCacheMemory<ENTRY>::lookup(Addr address) const 164{ 165 return &m_map[makeLineAddress(address)].m_entry; 166} 167 168template<class ENTRY> 169inline AccessPermission 170PerfectCacheMemory<ENTRY>::getPermission(Addr address) const 171{ 172 return m_map[makeLineAddress(address)].m_permission; 173} 174 175template<class ENTRY> 176inline void 177PerfectCacheMemory<ENTRY>::changePermission(Addr address, 178 AccessPermission new_perm) 179{ 180 Addr line_address = makeLineAddress(address); 181 PerfectCacheLineState<ENTRY>& line_state = m_map[line_address]; 182 line_state.m_permission = new_perm; 183} 184 185template<class ENTRY> 186inline void 187PerfectCacheMemory<ENTRY>::print(std::ostream& out) const 188{ 189} 190 191#endif // __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ 192