PerfectCacheMemory.hh revision 10441
16145SN/A/* 26145SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36145SN/A * All rights reserved. 46145SN/A * 56145SN/A * Redistribution and use in source and binary forms, with or without 66145SN/A * modification, are permitted provided that the following conditions are 76145SN/A * met: redistributions of source code must retain the above copyright 86145SN/A * notice, this list of conditions and the following disclaimer; 96145SN/A * redistributions in binary form must reproduce the above copyright 106145SN/A * notice, this list of conditions and the following disclaimer in the 116145SN/A * documentation and/or other materials provided with the distribution; 126145SN/A * neither the name of the copyright holders nor the names of its 136145SN/A * contributors may be used to endorse or promote products derived from 146145SN/A * this software without specific prior written permission. 156145SN/A * 166145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145SN/A */ 286145SN/A 2910441Snilay@cs.wisc.edu#ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ 3010441Snilay@cs.wisc.edu#define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ 316145SN/A 327455SN/A#include "base/hashmap.hh" 336154SN/A#include "mem/protocol/AccessPermission.hh" 346154SN/A#include "mem/ruby/common/Address.hh" 356145SN/A 366145SN/Atemplate<class ENTRY> 377039SN/Astruct PerfectCacheLineState 387039SN/A{ 397039SN/A PerfectCacheLineState() { m_permission = AccessPermission_NUM; } 407039SN/A AccessPermission m_permission; 417039SN/A ENTRY m_entry; 426145SN/A}; 436145SN/A 446145SN/Atemplate<class ENTRY> 457055SN/Ainline std::ostream& 467055SN/Aoperator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj) 476467SN/A{ 487039SN/A return out; 496467SN/A} 506467SN/A 516467SN/Atemplate<class ENTRY> 527039SN/Aclass PerfectCacheMemory 537039SN/A{ 547039SN/A public: 557039SN/A PerfectCacheMemory(); 566145SN/A 577039SN/A // tests to see if an address is present in the cache 587039SN/A bool isTagPresent(const Address& address) const; 596145SN/A 607039SN/A // Returns true if there is: 617039SN/A // a) a tag match on this address or there is 627039SN/A // b) an Invalid line in the same cache "way" 637039SN/A bool cacheAvail(const Address& address) const; 646145SN/A 657039SN/A // find an Invalid entry and sets the tag appropriate for the address 667039SN/A void allocate(const Address& address); 676145SN/A 687039SN/A void deallocate(const Address& address); 696145SN/A 707039SN/A // Returns with the physical address of the conflicting cache line 717039SN/A Address cacheProbe(const Address& newAddress) const; 726145SN/A 737039SN/A // looks an address up in the cache 747039SN/A ENTRY& lookup(const Address& address); 757039SN/A const ENTRY& lookup(const Address& address) const; 766145SN/A 777039SN/A // Get/Set permission of cache block 787039SN/A AccessPermission getPermission(const Address& address) const; 797039SN/A void changePermission(const Address& address, AccessPermission new_perm); 806145SN/A 817039SN/A // Print cache contents 827055SN/A void print(std::ostream& out) const; 836145SN/A 847039SN/A private: 857039SN/A // Private copy constructor and assignment operator 867039SN/A PerfectCacheMemory(const PerfectCacheMemory& obj); 877039SN/A PerfectCacheMemory& operator=(const PerfectCacheMemory& obj); 886145SN/A 897039SN/A // Data Members (m_prefix) 907455SN/A m5::hash_map<Address, PerfectCacheLineState<ENTRY> > m_map; 916145SN/A}; 926145SN/A 936145SN/Atemplate<class ENTRY> 947055SN/Ainline std::ostream& 957055SN/Aoperator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj) 966145SN/A{ 977039SN/A obj.print(out); 987055SN/A out << std::flush; 997039SN/A return out; 1006145SN/A} 1016145SN/A 1026145SN/Atemplate<class ENTRY> 1037039SN/Ainline 1046467SN/APerfectCacheMemory<ENTRY>::PerfectCacheMemory() 1056145SN/A{ 1066145SN/A} 1076145SN/A 1086145SN/A// tests to see if an address is present in the cache 1096145SN/Atemplate<class ENTRY> 1107039SN/Ainline bool 1117039SN/APerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const 1126145SN/A{ 1137455SN/A return m_map.count(line_address(address)) > 0; 1146145SN/A} 1156145SN/A 1166145SN/Atemplate<class ENTRY> 1177039SN/Ainline bool 1187039SN/APerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const 1196145SN/A{ 1207039SN/A return true; 1216145SN/A} 1226145SN/A 1236145SN/A// find an Invalid or already allocated entry and sets the tag 1246145SN/A// appropriate for the address 1256145SN/Atemplate<class ENTRY> 1267039SN/Ainline void 1277039SN/APerfectCacheMemory<ENTRY>::allocate(const Address& address) 1286145SN/A{ 1297039SN/A PerfectCacheLineState<ENTRY> line_state; 1308084SN/A line_state.m_permission = AccessPermission_Invalid; 1317039SN/A line_state.m_entry = ENTRY(); 1327455SN/A m_map[line_address(address)] = line_state; 1336145SN/A} 1346145SN/A 1356145SN/A// deallocate entry 1366145SN/Atemplate<class ENTRY> 1377039SN/Ainline void 1387039SN/APerfectCacheMemory<ENTRY>::deallocate(const Address& address) 1396145SN/A{ 1407039SN/A m_map.erase(line_address(address)); 1416145SN/A} 1426145SN/A 1436145SN/A// Returns with the physical address of the conflicting cache line 1446145SN/Atemplate<class ENTRY> 1457039SN/Ainline Address 1467039SN/APerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const 1476145SN/A{ 1487805SN/A panic("cacheProbe called in perfect cache"); 1497806SN/A return newAddress; 1506145SN/A} 1516145SN/A 1526145SN/A// looks an address up in the cache 1536145SN/Atemplate<class ENTRY> 1547039SN/Ainline ENTRY& 1557039SN/APerfectCacheMemory<ENTRY>::lookup(const Address& address) 1566145SN/A{ 1577455SN/A return m_map[line_address(address)].m_entry; 1586145SN/A} 1596145SN/A 1606145SN/A// looks an address up in the cache 1616145SN/Atemplate<class ENTRY> 1627039SN/Ainline const ENTRY& 1637039SN/APerfectCacheMemory<ENTRY>::lookup(const Address& address) const 1646145SN/A{ 1657455SN/A return m_map[line_address(address)].m_entry; 1666145SN/A} 1676145SN/A 1686145SN/Atemplate<class ENTRY> 1697039SN/Ainline AccessPermission 1707039SN/APerfectCacheMemory<ENTRY>::getPermission(const Address& address) const 1716145SN/A{ 1727455SN/A return m_map[line_address(address)].m_permission; 1736145SN/A} 1746145SN/A 1756145SN/Atemplate<class ENTRY> 1767039SN/Ainline void 1777039SN/APerfectCacheMemory<ENTRY>::changePermission(const Address& address, 1787039SN/A AccessPermission new_perm) 1796145SN/A{ 1807039SN/A Address line_address = address; 1817039SN/A line_address.makeLineAddress(); 1827455SN/A PerfectCacheLineState<ENTRY>& line_state = m_map[line_address]; 1837039SN/A line_state.m_permission = new_perm; 1846145SN/A} 1856145SN/A 1866145SN/Atemplate<class ENTRY> 1877039SN/Ainline void 1887055SN/APerfectCacheMemory<ENTRY>::print(std::ostream& out) const 1896145SN/A{ 1906145SN/A} 1916145SN/A 19210441Snilay@cs.wisc.edu#endif // __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ 193