16145SN/A/* 26145SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36145SN/A * All rights reserved. 46145SN/A * 56145SN/A * Redistribution and use in source and binary forms, with or without 66145SN/A * modification, are permitted provided that the following conditions are 76145SN/A * met: redistributions of source code must retain the above copyright 86145SN/A * notice, this list of conditions and the following disclaimer; 96145SN/A * redistributions in binary form must reproduce the above copyright 106145SN/A * notice, this list of conditions and the following disclaimer in the 116145SN/A * documentation and/or other materials provided with the distribution; 126145SN/A * neither the name of the copyright holders nor the names of its 136145SN/A * contributors may be used to endorse or promote products derived from 146145SN/A * this software without specific prior written permission. 156145SN/A * 166145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145SN/A */ 286145SN/A 2910441Snilay@cs.wisc.edu#ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ 3010441Snilay@cs.wisc.edu#define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ 316145SN/A 3211168Sandreas.hansson@arm.com#include <unordered_map> 3311168Sandreas.hansson@arm.com 346154SN/A#include "mem/ruby/common/Address.hh" 3514184Sgabeblack@google.com#include "mem/ruby/protocol/AccessPermission.hh" 366145SN/A 376145SN/Atemplate<class ENTRY> 387039SN/Astruct PerfectCacheLineState 397039SN/A{ 407039SN/A PerfectCacheLineState() { m_permission = AccessPermission_NUM; } 417039SN/A AccessPermission m_permission; 427039SN/A ENTRY m_entry; 436145SN/A}; 446145SN/A 456145SN/Atemplate<class ENTRY> 467055SN/Ainline std::ostream& 477055SN/Aoperator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj) 486467SN/A{ 497039SN/A return out; 506467SN/A} 516467SN/A 526467SN/Atemplate<class ENTRY> 537039SN/Aclass PerfectCacheMemory 547039SN/A{ 557039SN/A public: 567039SN/A PerfectCacheMemory(); 576145SN/A 587039SN/A // tests to see if an address is present in the cache 5911025Snilay@cs.wisc.edu bool isTagPresent(Addr address) const; 606145SN/A 617039SN/A // Returns true if there is: 627039SN/A // a) a tag match on this address or there is 637039SN/A // b) an Invalid line in the same cache "way" 6411025Snilay@cs.wisc.edu bool cacheAvail(Addr address) const; 656145SN/A 667039SN/A // find an Invalid entry and sets the tag appropriate for the address 6711025Snilay@cs.wisc.edu void allocate(Addr address); 686145SN/A 6911025Snilay@cs.wisc.edu void deallocate(Addr address); 706145SN/A 717039SN/A // Returns with the physical address of the conflicting cache line 7211025Snilay@cs.wisc.edu Addr cacheProbe(Addr newAddress) const; 736145SN/A 747039SN/A // looks an address up in the cache 7511025Snilay@cs.wisc.edu ENTRY* lookup(Addr address); 7611025Snilay@cs.wisc.edu const ENTRY* lookup(Addr address) const; 776145SN/A 787039SN/A // Get/Set permission of cache block 7911025Snilay@cs.wisc.edu AccessPermission getPermission(Addr address) const; 8011025Snilay@cs.wisc.edu void changePermission(Addr address, AccessPermission new_perm); 816145SN/A 827039SN/A // Print cache contents 837055SN/A void print(std::ostream& out) const; 846145SN/A 857039SN/A private: 867039SN/A // Private copy constructor and assignment operator 877039SN/A PerfectCacheMemory(const PerfectCacheMemory& obj); 887039SN/A PerfectCacheMemory& operator=(const PerfectCacheMemory& obj); 896145SN/A 907039SN/A // Data Members (m_prefix) 9111168Sandreas.hansson@arm.com std::unordered_map<Addr, PerfectCacheLineState<ENTRY> > m_map; 926145SN/A}; 936145SN/A 946145SN/Atemplate<class ENTRY> 957055SN/Ainline std::ostream& 967055SN/Aoperator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj) 976145SN/A{ 987039SN/A obj.print(out); 997055SN/A out << std::flush; 1007039SN/A return out; 1016145SN/A} 1026145SN/A 1036145SN/Atemplate<class ENTRY> 1047039SN/Ainline 1056467SN/APerfectCacheMemory<ENTRY>::PerfectCacheMemory() 1066145SN/A{ 1076145SN/A} 1086145SN/A 1096145SN/A// tests to see if an address is present in the cache 1106145SN/Atemplate<class ENTRY> 1117039SN/Ainline bool 11211025Snilay@cs.wisc.eduPerfectCacheMemory<ENTRY>::isTagPresent(Addr address) const 1136145SN/A{ 11411025Snilay@cs.wisc.edu return m_map.count(makeLineAddress(address)) > 0; 1156145SN/A} 1166145SN/A 1176145SN/Atemplate<class ENTRY> 1187039SN/Ainline bool 11911025Snilay@cs.wisc.eduPerfectCacheMemory<ENTRY>::cacheAvail(Addr address) const 1206145SN/A{ 1217039SN/A return true; 1226145SN/A} 1236145SN/A 1246145SN/A// find an Invalid or already allocated entry and sets the tag 1256145SN/A// appropriate for the address 1266145SN/Atemplate<class ENTRY> 1277039SN/Ainline void 12811025Snilay@cs.wisc.eduPerfectCacheMemory<ENTRY>::allocate(Addr address) 1296145SN/A{ 1307039SN/A PerfectCacheLineState<ENTRY> line_state; 1318084SN/A line_state.m_permission = AccessPermission_Invalid; 1327039SN/A line_state.m_entry = ENTRY(); 13311025Snilay@cs.wisc.edu m_map[makeLineAddress(address)] = line_state; 1346145SN/A} 1356145SN/A 1366145SN/A// deallocate entry 1376145SN/Atemplate<class ENTRY> 1387039SN/Ainline void 13911025Snilay@cs.wisc.eduPerfectCacheMemory<ENTRY>::deallocate(Addr address) 1406145SN/A{ 14111025Snilay@cs.wisc.edu m_map.erase(makeLineAddress(address)); 1426145SN/A} 1436145SN/A 1446145SN/A// Returns with the physical address of the conflicting cache line 1456145SN/Atemplate<class ENTRY> 14611025Snilay@cs.wisc.eduinline Addr 14711025Snilay@cs.wisc.eduPerfectCacheMemory<ENTRY>::cacheProbe(Addr newAddress) const 1486145SN/A{ 1497805SN/A panic("cacheProbe called in perfect cache"); 1507806SN/A return newAddress; 1516145SN/A} 1526145SN/A 1536145SN/A// looks an address up in the cache 1546145SN/Atemplate<class ENTRY> 15511020Sjthestness@gmail.cominline ENTRY* 15611025Snilay@cs.wisc.eduPerfectCacheMemory<ENTRY>::lookup(Addr address) 1576145SN/A{ 15811025Snilay@cs.wisc.edu return &m_map[makeLineAddress(address)].m_entry; 1596145SN/A} 1606145SN/A 1616145SN/A// looks an address up in the cache 1626145SN/Atemplate<class ENTRY> 16311020Sjthestness@gmail.cominline const ENTRY* 16411025Snilay@cs.wisc.eduPerfectCacheMemory<ENTRY>::lookup(Addr address) const 1656145SN/A{ 16611025Snilay@cs.wisc.edu return &m_map[makeLineAddress(address)].m_entry; 1676145SN/A} 1686145SN/A 1696145SN/Atemplate<class ENTRY> 1707039SN/Ainline AccessPermission 17111025Snilay@cs.wisc.eduPerfectCacheMemory<ENTRY>::getPermission(Addr address) const 1726145SN/A{ 17311025Snilay@cs.wisc.edu return m_map[makeLineAddress(address)].m_permission; 1746145SN/A} 1756145SN/A 1766145SN/Atemplate<class ENTRY> 1777039SN/Ainline void 17811025Snilay@cs.wisc.eduPerfectCacheMemory<ENTRY>::changePermission(Addr address, 1797039SN/A AccessPermission new_perm) 1806145SN/A{ 18111025Snilay@cs.wisc.edu Addr line_address = makeLineAddress(address); 1827455SN/A PerfectCacheLineState<ENTRY>& line_state = m_map[line_address]; 1837039SN/A line_state.m_permission = new_perm; 1846145SN/A} 1856145SN/A 1866145SN/Atemplate<class ENTRY> 1877039SN/Ainline void 1887055SN/APerfectCacheMemory<ENTRY>::print(std::ostream& out) const 1896145SN/A{ 1906145SN/A} 1916145SN/A 19210441Snilay@cs.wisc.edu#endif // __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ 193