CacheMemory.hh revision 9105 
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
30#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
31
32#include <iostream>
33#include <string>
34#include <vector>
35
36#include "base/hashmap.hh"
37#include "base/statistics.hh"
38#include "mem/protocol/CacheResourceType.hh"
39#include "mem/protocol/CacheRequestType.hh"
40#include "mem/protocol/GenericRequestType.hh"
41#include "mem/protocol/RubyRequest.hh"
42#include "mem/ruby/common/DataBlock.hh"
43#include "mem/ruby/profiler/CacheProfiler.hh"
44#include "mem/ruby/recorder/CacheRecorder.hh"
45#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
46#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
47#include "mem/ruby/system/BankedArray.hh"
48#include "mem/ruby/system/LRUPolicy.hh"
49#include "mem/ruby/system/PseudoLRUPolicy.hh"
50#include "params/RubyCache.hh"
51#include "sim/sim_object.hh"
52
53class CacheMemory : public SimObject
54{
55  public:
56    typedef RubyCacheParams Params;
57    CacheMemory(const Params *p);
58    ~CacheMemory();
59
60    void init();
61
62    // Public Methods
63    void printConfig(std::ostream& out);
64
65    // perform a cache access and see if we hit or not.  Return true on a hit.
66    bool tryCacheAccess(const Address& address, RubyRequestType type,
67                        DataBlock*& data_ptr);
68
69    // similar to above, but doesn't require full access check
70    bool testCacheAccess(const Address& address, RubyRequestType type,
71                         DataBlock*& data_ptr);
72
73    // tests to see if an address is present in the cache
74    bool isTagPresent(const Address& address) const;
75
76    // Returns true if there is:
77    //   a) a tag match on this address or there is
78    //   b) an unused line in the same cache "way"
79    bool cacheAvail(const Address& address) const;
80
81    // find an unused entry and sets the tag appropriate for the address
82    AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry);
83    void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
84    {
85        allocate(address, new_entry);
86    }
87
88    // Explicitly free up this address
89    void deallocate(const Address& address);
90
91    // Returns with the physical address of the conflicting cache line
92    Address cacheProbe(const Address& address) const;
93
94    // looks an address up in the cache
95    AbstractCacheEntry* lookup(const Address& address);
96    const AbstractCacheEntry* lookup(const Address& address) const;
97
98    int getLatency() const { return m_latency; }
99
100    // Hook for checkpointing the contents of the cache
101    void recordCacheContents(int cntrl, CacheRecorder* tr) const;
102
103    // Set this address to most recently used
104    void setMRU(const Address& address);
105
106    void profileMiss(const RubyRequest & msg);
107
108    void profileGenericRequest(GenericRequestType requestType,
109                               RubyAccessMode accessType,
110                               PrefetchBit pfBit);
111
112    void setLocked (const Address& addr, int context);
113    void clearLocked (const Address& addr);
114    bool isLocked (const Address& addr, int context);
115    // Print cache contents
116    void print(std::ostream& out) const;
117    void printData(std::ostream& out) const;
118
119    void clearStats() const;
120    void printStats(std::ostream& out) const;
121
122    void recordRequestType(CacheRequestType requestType);
123    void regStats();
124
125    Stats::Scalar numDataArrayReads;
126    Stats::Scalar numDataArrayWrites;
127    Stats::Scalar numTagArrayReads;
128    Stats::Scalar numTagArrayWrites;
129
130    bool checkResourceAvailable(CacheResourceType res, Address addr);
131
132    Stats::Scalar numTagArrayStalls;
133    Stats::Scalar numDataArrayStalls;
134  private:
135    // convert a Address to its location in the cache
136    Index addressToCacheSet(const Address& address) const;
137
138    // Given a cache tag: returns the index of the tag in a set.
139    // returns -1 if the tag is not found.
140    int findTagInSet(Index line, const Address& tag) const;
141    int findTagInSetIgnorePermissions(Index cacheSet,
142                                      const Address& tag) const;
143
144    // Private copy constructor and assignment operator
145    CacheMemory(const CacheMemory& obj);
146    CacheMemory& operator=(const CacheMemory& obj);
147
148  private:
149    const std::string m_cache_name;
150    int m_latency;
151
152    // Data Members (m_prefix)
153    bool m_is_instruction_only_cache;
154
155    // The first index is the # of cache lines.
156    // The second index is the the amount associativity.
157    m5::hash_map<Address, int> m_tag_index;
158    std::vector<std::vector<AbstractCacheEntry*> > m_cache;
159
160    AbstractReplacementPolicy *m_replacementPolicy_ptr;
161
162    CacheProfiler* m_profiler_ptr;
163
164    BankedArray dataArray;
165    BankedArray tagArray;
166
167    int m_cache_size;
168    std::string m_policy;
169    int m_cache_num_sets;
170    int m_cache_num_set_bits;
171    int m_cache_assoc;
172    int m_start_index_bit;
173    bool m_resource_stalls;
174};
175
176#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
177
178