CacheMemory.hh revision 7055
12239SN/A/* 22239SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 32239SN/A * All rights reserved. 42239SN/A * 52239SN/A * Redistribution and use in source and binary forms, with or without 62239SN/A * modification, are permitted provided that the following conditions are 72239SN/A * met: redistributions of source code must retain the above copyright 82239SN/A * notice, this list of conditions and the following disclaimer; 92239SN/A * redistributions in binary form must reproduce the above copyright 102239SN/A * notice, this list of conditions and the following disclaimer in the 112239SN/A * documentation and/or other materials provided with the distribution; 122239SN/A * neither the name of the copyright holders nor the names of its 132239SN/A * contributors may be used to endorse or promote products derived from 142239SN/A * this software without specific prior written permission. 152239SN/A * 162239SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172239SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182239SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192239SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202239SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212239SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222239SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232239SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242239SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252239SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262239SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292239SN/A#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 302239SN/A#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 312239SN/A 322239SN/A#include <iostream> 332239SN/A#include <string> 342239SN/A#include <vector> 352239SN/A 362239SN/A#include "base/hashmap.hh" 372680Sktlim@umich.edu#include "mem/gems_common/Vector.hh" 382239SN/A#include "mem/protocol/AccessPermission.hh" 392239SN/A#include "mem/protocol/CacheMsg.hh" 402239SN/A#include "mem/protocol/CacheRequestType.hh" 412239SN/A#include "mem/protocol/MachineType.hh" 422239SN/A#include "mem/ruby/common/Address.hh" 432680Sktlim@umich.edu#include "mem/ruby/common/DataBlock.hh" 442239SN/A#include "mem/ruby/common/Global.hh" 452239SN/A#include "mem/ruby/profiler/CacheProfiler.hh" 462239SN/A#include "mem/ruby/recorder/CacheRecorder.hh" 472239SN/A#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 482239SN/A#include "mem/ruby/slicc_interface/AbstractController.hh" 492239SN/A#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 502239SN/A#include "mem/ruby/system/LRUPolicy.hh" 512239SN/A#include "mem/ruby/system/PseudoLRUPolicy.hh" 522680Sktlim@umich.edu#include "mem/ruby/system/System.hh" 532239SN/A#include "params/RubyCache.hh" 542239SN/A#include "sim/sim_object.hh" 552239SN/A 562239SN/Aclass CacheMemory : public SimObject 572239SN/A{ 582239SN/A public: 592239SN/A typedef RubyCacheParams Params; 602239SN/A CacheMemory(const Params *p); 612239SN/A ~CacheMemory(); 622239SN/A 632239SN/A void init(); 642680Sktlim@umich.edu 652239SN/A // Public Methods 662239SN/A void printConfig(std::ostream& out); 672239SN/A 682239SN/A // perform a cache access and see if we hit or not. Return true on a hit. 692239SN/A bool tryCacheAccess(const Address& address, CacheRequestType type, 702239SN/A DataBlock*& data_ptr); 712239SN/A 722239SN/A // similar to above, but doesn't require full access check 732680Sktlim@umich.edu bool testCacheAccess(const Address& address, CacheRequestType type, 742239SN/A DataBlock*& data_ptr); 752239SN/A 762239SN/A // tests to see if an address is present in the cache 772680Sktlim@umich.edu bool isTagPresent(const Address& address) const; 782239SN/A 792239SN/A // Returns true if there is: 802239SN/A // a) a tag match on this address or there is 812239SN/A // b) an unused line in the same cache "way" 822680Sktlim@umich.edu bool cacheAvail(const Address& address) const; 832239SN/A 842239SN/A // find an unused entry and sets the tag appropriate for the address 852239SN/A void allocate(const Address& address, AbstractCacheEntry* new_entry); 862680Sktlim@umich.edu 872680Sktlim@umich.edu // Explicitly free up this address 882239SN/A void deallocate(const Address& address); 892239SN/A 902239SN/A // Returns with the physical address of the conflicting cache line 912239SN/A Address cacheProbe(const Address& address) const; 922239SN/A 932239SN/A // looks an address up in the cache 942239SN/A AbstractCacheEntry& lookup(const Address& address); 952239SN/A const AbstractCacheEntry& lookup(const Address& address) const; 962239SN/A 972239SN/A // Get/Set permission of cache block 982239SN/A AccessPermission getPermission(const Address& address) const; 992239SN/A void changePermission(const Address& address, AccessPermission new_perm); 1002239SN/A 1012239SN/A int getLatency() const { return m_latency; } 1022239SN/A 1032239SN/A // Hook for checkpointing the contents of the cache 1042239SN/A void recordCacheContents(CacheRecorder& tr) const; 1052239SN/A void 1062239SN/A setAsInstructionCache(bool is_icache) 1072239SN/A { 1082239SN/A m_is_instruction_only_cache = is_icache; 1092680Sktlim@umich.edu } 1102239SN/A 1112239SN/A // Set this address to most recently used 1122239SN/A void setMRU(const Address& address); 1132239SN/A 1142239SN/A void profileMiss(const CacheMsg & msg); 1152239SN/A 1162239SN/A void getMemoryValue(const Address& addr, char* value, 1172680Sktlim@umich.edu unsigned int size_in_bytes); 1182239SN/A void setMemoryValue(const Address& addr, char* value, 1192239SN/A unsigned int size_in_bytes); 1202239SN/A 1212239SN/A void setLocked (const Address& addr, int context); 122 void clearLocked (const Address& addr); 123 bool isLocked (const Address& addr, int context); 124 // Print cache contents 125 void print(std::ostream& out) const; 126 void printData(std::ostream& out) const; 127 128 void clearStats() const; 129 void printStats(std::ostream& out) const; 130 131 private: 132 // convert a Address to its location in the cache 133 Index addressToCacheSet(const Address& address) const; 134 135 // Given a cache tag: returns the index of the tag in a set. 136 // returns -1 if the tag is not found. 137 int findTagInSet(Index line, const Address& tag) const; 138 int findTagInSetIgnorePermissions(Index cacheSet, 139 const Address& tag) const; 140 141 // Private copy constructor and assignment operator 142 CacheMemory(const CacheMemory& obj); 143 CacheMemory& operator=(const CacheMemory& obj); 144 145 private: 146 const std::string m_cache_name; 147 int m_latency; 148 149 // Data Members (m_prefix) 150 bool m_is_instruction_only_cache; 151 bool m_is_data_only_cache; 152 153 // The first index is the # of cache lines. 154 // The second index is the the amount associativity. 155 m5::hash_map<Address, int> m_tag_index; 156 Vector<Vector<AbstractCacheEntry*> > m_cache; 157 Vector<Vector<int> > m_locked; 158 159 AbstractReplacementPolicy *m_replacementPolicy_ptr; 160 161 CacheProfiler* m_profiler_ptr; 162 163 int m_cache_size; 164 std::string m_policy; 165 int m_cache_num_sets; 166 int m_cache_num_set_bits; 167 int m_cache_assoc; 168}; 169 170#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 171 172