CacheMemory.hh revision 6876
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 * CacheMemory.hh 31 * 32 * Description: 33 * 34 * $Id: CacheMemory.hh,v 3.7 2004/06/18 20:15:15 beckmann Exp $ 35 * 36 */ 37 38#ifndef CACHEMEMORY_H 39#define CACHEMEMORY_H 40 41#include "sim/sim_object.hh" 42#include "params/RubyCache.hh" 43 44#include "mem/ruby/common/Global.hh" 45#include "mem/protocol/AccessPermission.hh" 46#include "mem/ruby/common/Address.hh" 47#include "mem/ruby/recorder/CacheRecorder.hh" 48#include "mem/protocol/CacheRequestType.hh" 49#include "mem/gems_common/Vector.hh" 50#include "mem/ruby/common/DataBlock.hh" 51#include "mem/protocol/MachineType.hh" 52#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 53#include "mem/ruby/system/PseudoLRUPolicy.hh" 54#include "mem/ruby/system/LRUPolicy.hh" 55#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 56#include "mem/ruby/system/System.hh" 57#include "mem/ruby/slicc_interface/AbstractController.hh" 58#include "mem/ruby/profiler/CacheProfiler.hh" 59#include "mem/protocol/CacheMsg.hh" 60#include "base/hashmap.hh" 61#include <vector> 62 63class CacheMemory : public SimObject { 64public: 65 66 typedef RubyCacheParams Params; 67 // Constructors 68 CacheMemory(const Params *p); 69 // CacheMemory(const string & name); 70 void init(); 71 72 // Destructor 73 ~CacheMemory(); 74 75 // factory 76 // static CacheMemory* createCache(int level, int num, char split_type, AbstractCacheEntry* (*entry_factory)()); 77 // static CacheMemory* getCache(int cache_id); 78 79 // Public Methods 80 void printConfig(ostream& out); 81 82 // perform a cache access and see if we hit or not. Return true on a hit. 83 bool tryCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr); 84 85 // similar to above, but doesn't require full access check 86 bool testCacheAccess(const Address& address, CacheRequestType type, DataBlock*& data_ptr); 87 88 // tests to see if an address is present in the cache 89 bool isTagPresent(const Address& address) const; 90 91 // Returns true if there is: 92 // a) a tag match on this address or there is 93 // b) an unused line in the same cache "way" 94 bool cacheAvail(const Address& address) const; 95 96 // find an unused entry and sets the tag appropriate for the address 97 void allocate(const Address& address, AbstractCacheEntry* new_entry); 98 99 // Explicitly free up this address 100 void deallocate(const Address& address); 101 102 // Returns with the physical address of the conflicting cache line 103 Address cacheProbe(const Address& address) const; 104 105 // looks an address up in the cache 106 AbstractCacheEntry& lookup(const Address& address); 107 const AbstractCacheEntry& lookup(const Address& address) const; 108 109 // Get/Set permission of cache block 110 AccessPermission getPermission(const Address& address) const; 111 void changePermission(const Address& address, AccessPermission new_perm); 112 113 static int numberOfLastLevelCaches(); 114 115 int getLatency() const { return m_latency; } 116 117 // Hook for checkpointing the contents of the cache 118 void recordCacheContents(CacheRecorder& tr) const; 119 void setAsInstructionCache(bool is_icache) { m_is_instruction_only_cache = is_icache; } 120 121 // Set this address to most recently used 122 void setMRU(const Address& address); 123 124 void profileMiss(const CacheMsg & msg); 125 126 void getMemoryValue(const Address& addr, char* value, 127 unsigned int size_in_bytes ); 128 void setMemoryValue(const Address& addr, char* value, 129 unsigned int size_in_bytes ); 130 131 void setLocked (const Address& addr, int context); 132 void clearLocked (const Address& addr); 133 bool isLocked (const Address& addr, int context); 134 // Print cache contents 135 void print(ostream& out) const; 136 void printData(ostream& out) const; 137 138 void clearStats() const; 139 void printStats(ostream& out) const; 140 141private: 142 // Private Methods 143 144 // convert a Address to its location in the cache 145 Index addressToCacheSet(const Address& address) const; 146 147 // Given a cache tag: returns the index of the tag in a set. 148 // returns -1 if the tag is not found. 149 int findTagInSet(Index line, const Address& tag) const; 150 int findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const; 151 152 // Private copy constructor and assignment operator 153 CacheMemory(const CacheMemory& obj); 154 CacheMemory& operator=(const CacheMemory& obj); 155 156private: 157 const string m_cache_name; 158 AbstractController* m_controller; 159 int m_latency; 160 161 // Data Members (m_prefix) 162 bool m_is_instruction_only_cache; 163 bool m_is_data_only_cache; 164 165 // The first index is the # of cache lines. 166 // The second index is the the amount associativity. 167 m5::hash_map<Address, int> m_tag_index; 168 Vector<Vector<AbstractCacheEntry*> > m_cache; 169 Vector<Vector<int> > m_locked; 170 171 AbstractReplacementPolicy *m_replacementPolicy_ptr; 172 173 CacheProfiler* m_profiler_ptr; 174 175 int m_cache_num_sets; 176 int m_cache_num_set_bits; 177 int m_cache_assoc; 178 179 static Vector< CacheMemory* > m_all_caches; 180 181 static int m_num_last_level_caches; 182 static MachineType m_last_level_machine_type; 183 184}; 185 186#endif //CACHEMEMORY_H 187 188