CacheMemory.hh revision 10314
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IN NO EVENT SHALL THE COPYRIGHT 207087Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217087Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224159Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237087Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244159Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254159Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264159Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274159Sgblack@eecs.umich.edu */ 284159Sgblack@eecs.umich.edu 294159Sgblack@eecs.umich.edu#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 304159Sgblack@eecs.umich.edu#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 314159Sgblack@eecs.umich.edu 324159Sgblack@eecs.umich.edu#include <string> 334159Sgblack@eecs.umich.edu#include <vector> 344159Sgblack@eecs.umich.edu 354159Sgblack@eecs.umich.edu#include "base/hashmap.hh" 364159Sgblack@eecs.umich.edu#include "base/statistics.hh" 374159Sgblack@eecs.umich.edu#include "mem/protocol/CacheRequestType.hh" 384159Sgblack@eecs.umich.edu#include "mem/protocol/CacheResourceType.hh" 394159Sgblack@eecs.umich.edu#include "mem/protocol/RubyRequest.hh" 404159Sgblack@eecs.umich.edu#include "mem/ruby/common/DataBlock.hh" 414159Sgblack@eecs.umich.edu#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 424159Sgblack@eecs.umich.edu#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 435124Sgblack@eecs.umich.edu#include "mem/ruby/structures/BankedArray.hh" 445124Sgblack@eecs.umich.edu#include "mem/ruby/structures/LRUPolicy.hh" 455124Sgblack@eecs.umich.edu#include "mem/ruby/structures/PseudoLRUPolicy.hh" 465237Sgblack@eecs.umich.edu#include "mem/ruby/system/CacheRecorder.hh" 474159Sgblack@eecs.umich.edu#include "params/RubyCache.hh" 486216Snate@binkert.org#include "sim/sim_object.hh" 498953Sgblack@eecs.umich.edu 504159Sgblack@eecs.umich.educlass CacheMemory : public SimObject 515124Sgblack@eecs.umich.edu{ 525124Sgblack@eecs.umich.edu public: 534159Sgblack@eecs.umich.edu typedef RubyCacheParams Params; 544159Sgblack@eecs.umich.edu CacheMemory(const Params *p); 558953Sgblack@eecs.umich.edu ~CacheMemory(); 568953Sgblack@eecs.umich.edu 578953Sgblack@eecs.umich.edu void init(); 588953Sgblack@eecs.umich.edu 598953Sgblack@eecs.umich.edu // Public Methods 608953Sgblack@eecs.umich.edu // perform a cache access and see if we hit or not. Return true on a hit. 618953Sgblack@eecs.umich.edu bool tryCacheAccess(const Address& address, RubyRequestType type, 625237Sgblack@eecs.umich.edu DataBlock*& data_ptr); 635237Sgblack@eecs.umich.edu 645237Sgblack@eecs.umich.edu // similar to above, but doesn't require full access check 655237Sgblack@eecs.umich.edu bool testCacheAccess(const Address& address, RubyRequestType type, 665237Sgblack@eecs.umich.edu DataBlock*& data_ptr); 675237Sgblack@eecs.umich.edu 685237Sgblack@eecs.umich.edu // tests to see if an address is present in the cache 695237Sgblack@eecs.umich.edu bool isTagPresent(const Address& address) const; 705237Sgblack@eecs.umich.edu 715237Sgblack@eecs.umich.edu // Returns true if there is: 725237Sgblack@eecs.umich.edu // a) a tag match on this address or there is 735237Sgblack@eecs.umich.edu // b) an unused line in the same cache "way" 745237Sgblack@eecs.umich.edu bool cacheAvail(const Address& address) const; 754159Sgblack@eecs.umich.edu 765124Sgblack@eecs.umich.edu // find an unused entry and sets the tag appropriate for the address 774159Sgblack@eecs.umich.edu AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry); 785124Sgblack@eecs.umich.edu void allocateVoid(const Address& address, AbstractCacheEntry* new_entry) 795184Sgblack@eecs.umich.edu { 805184Sgblack@eecs.umich.edu allocate(address, new_entry); 815184Sgblack@eecs.umich.edu } 825184Sgblack@eecs.umich.edu 838953Sgblack@eecs.umich.edu // Explicitly free up this address 848953Sgblack@eecs.umich.edu void deallocate(const Address& address); 855184Sgblack@eecs.umich.edu 865124Sgblack@eecs.umich.edu // Returns with the physical address of the conflicting cache line 875124Sgblack@eecs.umich.edu Address cacheProbe(const Address& address) const; 885184Sgblack@eecs.umich.edu 895124Sgblack@eecs.umich.edu // looks an address up in the cache 905124Sgblack@eecs.umich.edu AbstractCacheEntry* lookup(const Address& address); 915124Sgblack@eecs.umich.edu const AbstractCacheEntry* lookup(const Address& address) const; 925124Sgblack@eecs.umich.edu 935124Sgblack@eecs.umich.edu Cycles getLatency() const { return m_latency; } 945124Sgblack@eecs.umich.edu 955124Sgblack@eecs.umich.edu // Hook for checkpointing the contents of the cache 965124Sgblack@eecs.umich.edu void recordCacheContents(int cntrl, CacheRecorder* tr) const; 975124Sgblack@eecs.umich.edu 985124Sgblack@eecs.umich.edu // Set this address to most recently used 995124Sgblack@eecs.umich.edu void setMRU(const Address& address); 1005124Sgblack@eecs.umich.edu 1015124Sgblack@eecs.umich.edu void setLocked (const Address& addr, int context); 1028953Sgblack@eecs.umich.edu void clearLocked (const Address& addr); 1038953Sgblack@eecs.umich.edu bool isLocked (const Address& addr, int context); 1048953Sgblack@eecs.umich.edu 1058953Sgblack@eecs.umich.edu // Print cache contents 1065124Sgblack@eecs.umich.edu void print(std::ostream& out) const; 1075184Sgblack@eecs.umich.edu void printData(std::ostream& out) const; 1085184Sgblack@eecs.umich.edu 1095124Sgblack@eecs.umich.edu void regStats(); 1105877Shsul@eecs.umich.edu bool checkResourceAvailable(CacheResourceType res, Address addr); 1115877Shsul@eecs.umich.edu void recordRequestType(CacheRequestType requestType); 1125877Shsul@eecs.umich.edu 1135877Shsul@eecs.umich.edu public: 1145877Shsul@eecs.umich.edu Stats::Scalar m_demand_hits; 1155877Shsul@eecs.umich.edu Stats::Scalar m_demand_misses; 1165184Sgblack@eecs.umich.edu Stats::Formula m_demand_accesses; 1175184Sgblack@eecs.umich.edu 1185184Sgblack@eecs.umich.edu Stats::Scalar m_sw_prefetches; 1195184Sgblack@eecs.umich.edu Stats::Scalar m_hw_prefetches; 1205124Sgblack@eecs.umich.edu Stats::Formula m_prefetches; 1219115SBrad.Beckmann@amd.com 1229115SBrad.Beckmann@amd.com Stats::Vector m_accessModeType; 1239115SBrad.Beckmann@amd.com 1249115SBrad.Beckmann@amd.com Stats::Scalar numDataArrayReads; 1259115SBrad.Beckmann@amd.com Stats::Scalar numDataArrayWrites; 1269115SBrad.Beckmann@amd.com Stats::Scalar numTagArrayReads; 1275124Sgblack@eecs.umich.edu Stats::Scalar numTagArrayWrites; 1285124Sgblack@eecs.umich.edu 1294159Sgblack@eecs.umich.edu Stats::Scalar numTagArrayStalls; 1304159Sgblack@eecs.umich.edu Stats::Scalar numDataArrayStalls; 1314159Sgblack@eecs.umich.edu 1324159Sgblack@eecs.umich.edu private: 133 // convert a Address to its location in the cache 134 int64 addressToCacheSet(const Address& address) const; 135 136 // Given a cache tag: returns the index of the tag in a set. 137 // returns -1 if the tag is not found. 138 int findTagInSet(int64 line, const Address& tag) const; 139 int findTagInSetIgnorePermissions(int64 cacheSet, 140 const Address& tag) const; 141 142 // Private copy constructor and assignment operator 143 CacheMemory(const CacheMemory& obj); 144 CacheMemory& operator=(const CacheMemory& obj); 145 146 private: 147 Cycles m_latency; 148 149 // Data Members (m_prefix) 150 bool m_is_instruction_only_cache; 151 152 // The first index is the # of cache lines. 153 // The second index is the the amount associativity. 154 m5::hash_map<Address, int> m_tag_index; 155 std::vector<std::vector<AbstractCacheEntry*> > m_cache; 156 157 AbstractReplacementPolicy *m_replacementPolicy_ptr; 158 159 BankedArray dataArray; 160 BankedArray tagArray; 161 162 int m_cache_size; 163 std::string m_policy; 164 int m_cache_num_sets; 165 int m_cache_num_set_bits; 166 int m_cache_assoc; 167 int m_start_index_bit; 168 bool m_resource_stalls; 169}; 170 171std::ostream& operator<<(std::ostream& out, const CacheMemory& obj); 172 173#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 174