CacheMemory.hh revision 9692
16145SN/A/* 28683SN/A * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 36145SN/A * All rights reserved. 46145SN/A * 56145SN/A * Redistribution and use in source and binary forms, with or without 66145SN/A * modification, are permitted provided that the following conditions are 76145SN/A * met: redistributions of source code must retain the above copyright 86145SN/A * notice, this list of conditions and the following disclaimer; 96145SN/A * redistributions in binary form must reproduce the above copyright 106145SN/A * notice, this list of conditions and the following disclaimer in the 116145SN/A * documentation and/or other materials provided with the distribution; 126145SN/A * neither the name of the copyright holders nor the names of its 136145SN/A * contributors may be used to endorse or promote products derived from 146145SN/A * this software without specific prior written permission. 156145SN/A * 166145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145SN/A */ 286145SN/A 2910441Snilay@cs.wisc.edu#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 3010441Snilay@cs.wisc.edu#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 316145SN/A 327055SN/A#include <string> 336145SN/A#include <vector> 346145SN/A 357039SN/A#include "base/hashmap.hh" 369104SN/A#include "base/statistics.hh" 3710301Snilay@cs.wisc.edu#include "mem/protocol/CacheResourceType.hh" 389105SN/A#include "mem/protocol/CacheRequestType.hh" 398174SN/A#include "mem/protocol/RubyRequest.hh" 407039SN/A#include "mem/ruby/common/DataBlock.hh" 417039SN/A#include "mem/ruby/recorder/CacheRecorder.hh" 427039SN/A#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 4310301Snilay@cs.wisc.edu#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 4410301Snilay@cs.wisc.edu#include "mem/ruby/system/BankedArray.hh" 4510301Snilay@cs.wisc.edu#include "mem/ruby/system/LRUPolicy.hh" 4610301Snilay@cs.wisc.edu#include "mem/ruby/system/PseudoLRUPolicy.hh" 477039SN/A#include "params/RubyCache.hh" 487039SN/A#include "sim/sim_object.hh" 496145SN/A 507039SN/Aclass CacheMemory : public SimObject 517039SN/A{ 527039SN/A public: 536876SN/A typedef RubyCacheParams Params; 547039SN/A CacheMemory(const Params *p); 557039SN/A ~CacheMemory(); 566145SN/A 577039SN/A void init(); 586145SN/A 597039SN/A // Public Methods 607039SN/A // perform a cache access and see if we hit or not. Return true on a hit. 618165SN/A bool tryCacheAccess(const Address& address, RubyRequestType type, 627039SN/A DataBlock*& data_ptr); 636145SN/A 647039SN/A // similar to above, but doesn't require full access check 658165SN/A bool testCacheAccess(const Address& address, RubyRequestType type, 667039SN/A DataBlock*& data_ptr); 676145SN/A 687039SN/A // tests to see if an address is present in the cache 697039SN/A bool isTagPresent(const Address& address) const; 706145SN/A 717039SN/A // Returns true if there is: 727039SN/A // a) a tag match on this address or there is 737039SN/A // b) an unused line in the same cache "way" 747039SN/A bool cacheAvail(const Address& address) const; 756145SN/A 767039SN/A // find an unused entry and sets the tag appropriate for the address 777839SN/A AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry); 788193SN/A void allocateVoid(const Address& address, AbstractCacheEntry* new_entry) 798193SN/A { 808193SN/A allocate(address, new_entry); 818193SN/A } 826145SN/A 837039SN/A // Explicitly free up this address 847039SN/A void deallocate(const Address& address); 856145SN/A 867039SN/A // Returns with the physical address of the conflicting cache line 877039SN/A Address cacheProbe(const Address& address) const; 886145SN/A 897039SN/A // looks an address up in the cache 907839SN/A AbstractCacheEntry* lookup(const Address& address); 917839SN/A const AbstractCacheEntry* lookup(const Address& address) const; 926145SN/A 939499SN/A Cycles getLatency() const { return m_latency; } 946285SN/A 957039SN/A // Hook for checkpointing the contents of the cache 968683SN/A void recordCacheContents(int cntrl, CacheRecorder* tr) const; 976145SN/A 987039SN/A // Set this address to most recently used 997039SN/A void setMRU(const Address& address); 1006145SN/A 1017039SN/A void setLocked (const Address& addr, int context); 1027039SN/A void clearLocked (const Address& addr); 1037039SN/A bool isLocked (const Address& addr, int context); 1049692SN/A 1057039SN/A // Print cache contents 1067055SN/A void print(std::ostream& out) const; 1077055SN/A void printData(std::ostream& out) const; 1086145SN/A 1099692SN/A void regStats(); 1109692SN/A bool checkResourceAvailable(CacheResourceType res, Address addr); 1119692SN/A void recordRequestType(CacheRequestType requestType); 1126374SN/A 1139692SN/A public: 1149692SN/A Stats::Scalar m_demand_hits; 1159692SN/A Stats::Scalar m_demand_misses; 1169692SN/A Stats::Formula m_demand_accesses; 1179692SN/A 1189692SN/A Stats::Scalar m_sw_prefetches; 1199692SN/A Stats::Scalar m_hw_prefetches; 1209692SN/A Stats::Formula m_prefetches; 1219692SN/A 1229692SN/A Stats::Vector m_accessModeType; 1239104SN/A 1249104SN/A Stats::Scalar numDataArrayReads; 1259104SN/A Stats::Scalar numDataArrayWrites; 1269104SN/A Stats::Scalar numTagArrayReads; 1279104SN/A Stats::Scalar numTagArrayWrites; 1289104SN/A 1299105SN/A Stats::Scalar numTagArrayStalls; 1309105SN/A Stats::Scalar numDataArrayStalls; 1319692SN/A 1327039SN/A private: 1337039SN/A // convert a Address to its location in the cache 13410314Snilay@cs.wisc.edu Index addressToCacheSet(const Address& address) const; 1356145SN/A 1367039SN/A // Given a cache tag: returns the index of the tag in a set. 1377039SN/A // returns -1 if the tag is not found. 13810314Snilay@cs.wisc.edu int findTagInSet(Index line, const Address& tag) const; 13910314Snilay@cs.wisc.edu int findTagInSetIgnorePermissions(Index cacheSet, 1407039SN/A const Address& tag) const; 1416145SN/A 1427039SN/A // Private copy constructor and assignment operator 1437039SN/A CacheMemory(const CacheMemory& obj); 1447039SN/A CacheMemory& operator=(const CacheMemory& obj); 1456145SN/A 1467039SN/A private: 1479499SN/A const std::string m_cache_name; 1486145SN/A Cycles m_latency; 1497039SN/A 1507039SN/A // Data Members (m_prefix) 1516285SN/A bool m_is_instruction_only_cache; 1527039SN/A 1537039SN/A // The first index is the # of cache lines. 1547039SN/A // The second index is the the amount associativity. 1557454SN/A m5::hash_map<Address, int> m_tag_index; 1566145SN/A std::vector<std::vector<AbstractCacheEntry*> > m_cache; 1577039SN/A 1586145SN/A AbstractReplacementPolicy *m_replacementPolicy_ptr; 1599105SN/A 1609105SN/A BankedArray dataArray; 1619105SN/A BankedArray tagArray; 1627039SN/A 1637055SN/A int m_cache_size; 1647039SN/A std::string m_policy; 1657039SN/A int m_cache_num_sets; 1667039SN/A int m_cache_num_set_bits; 1677564SN/A int m_cache_assoc; 1689105SN/A int m_start_index_bit; 1696145SN/A bool m_resource_stalls; 1706145SN/A}; 1719554SN/A 1729554SN/Astd::ostream& operator<<(std::ostream& out, const CacheMemory& obj); 17310441Snilay@cs.wisc.edu 174#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 175