CacheMemory.hh revision 9554
12SN/A/* 21762SN/A * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 302665Ssaidi@eecs.umich.edu#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 312SN/A 322SN/A#include <string> 332SN/A#include <vector> 342SN/A 352SN/A#include "base/hashmap.hh" 362SN/A#include "base/statistics.hh" 3775SN/A#include "mem/protocol/CacheResourceType.hh" 382SN/A#include "mem/protocol/CacheRequestType.hh" 392439SN/A#include "mem/protocol/GenericRequestType.hh" 402439SN/A#include "mem/protocol/RubyRequest.hh" 41603SN/A#include "mem/ruby/common/DataBlock.hh" 422986Sgblack@eecs.umich.edu#include "mem/ruby/profiler/CacheProfiler.hh" 43603SN/A#include "mem/ruby/recorder/CacheRecorder.hh" 442520SN/A#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 452378SN/A#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 462378SN/A#include "mem/ruby/system/BankedArray.hh" 47722SN/A#include "mem/ruby/system/LRUPolicy.hh" 482521SN/A#include "mem/ruby/system/PseudoLRUPolicy.hh" 492378SN/A#include "params/RubyCache.hh" 50312SN/A#include "sim/sim_object.hh" 511634SN/A 522680Sktlim@umich.educlass CacheMemory : public SimObject 531634SN/A{ 542521SN/A public: 552378SN/A typedef RubyCacheParams Params; 562378SN/A CacheMemory(const Params *p); 57803SN/A ~CacheMemory(); 582378SN/A 592SN/A void init(); 602378SN/A 612SN/A // Public Methods 622SN/A // perform a cache access and see if we hit or not. Return true on a hit. 632SN/A bool tryCacheAccess(const Address& address, RubyRequestType type, 64603SN/A DataBlock*& data_ptr); 652901Ssaidi@eecs.umich.edu 662901Ssaidi@eecs.umich.edu // similar to above, but doesn't require full access check 672901Ssaidi@eecs.umich.edu bool testCacheAccess(const Address& address, RubyRequestType type, 682901Ssaidi@eecs.umich.edu DataBlock*& data_ptr); 692901Ssaidi@eecs.umich.edu 702901Ssaidi@eecs.umich.edu // tests to see if an address is present in the cache 712902Ssaidi@eecs.umich.edu bool isTagPresent(const Address& address) const; 722902Ssaidi@eecs.umich.edu 732901Ssaidi@eecs.umich.edu // Returns true if there is: 742901Ssaidi@eecs.umich.edu // a) a tag match on this address or there is 752901Ssaidi@eecs.umich.edu // b) an unused line in the same cache "way" 762901Ssaidi@eecs.umich.edu bool cacheAvail(const Address& address) const; 772901Ssaidi@eecs.umich.edu 782901Ssaidi@eecs.umich.edu // find an unused entry and sets the tag appropriate for the address 792901Ssaidi@eecs.umich.edu AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry); 802901Ssaidi@eecs.umich.edu void allocateVoid(const Address& address, AbstractCacheEntry* new_entry) 812901Ssaidi@eecs.umich.edu { 822521SN/A allocate(address, new_entry); 832SN/A } 842SN/A 852680Sktlim@umich.edu // Explicitly free up this address 861806SN/A void deallocate(const Address& address); 871806SN/A 881806SN/A // Returns with the physical address of the conflicting cache line 891806SN/A Address cacheProbe(const Address& address) const; 902680Sktlim@umich.edu 911806SN/A // looks an address up in the cache 921806SN/A AbstractCacheEntry* lookup(const Address& address); 931806SN/A const AbstractCacheEntry* lookup(const Address& address) const; 941806SN/A 95180SN/A Cycles getLatency() const { return m_latency; } 962378SN/A 972378SN/A // Hook for checkpointing the contents of the cache 982378SN/A void recordCacheContents(int cntrl, CacheRecorder* tr) const; 992378SN/A 1002520SN/A // Set this address to most recently used 1012520SN/A void setMRU(const Address& address); 1022520SN/A 1032521SN/A void profileMiss(const RubyRequest & msg); 1042520SN/A 1051885SN/A void profileGenericRequest(GenericRequestType requestType, 1061070SN/A RubyAccessMode accessType, 107954SN/A PrefetchBit pfBit); 1081070SN/A 1091070SN/A void setLocked (const Address& addr, int context); 1101070SN/A void clearLocked (const Address& addr); 1111070SN/A bool isLocked (const Address& addr, int context); 1121070SN/A // Print cache contents 1131070SN/A void print(std::ostream& out) const; 1141070SN/A void printData(std::ostream& out) const; 1151070SN/A 1161070SN/A void clearStats() const; 1171070SN/A void printStats(std::ostream& out) const; 1181070SN/A 1191070SN/A void recordRequestType(CacheRequestType requestType); 1202378SN/A void regStats(); 1212378SN/A 1222378SN/A Stats::Scalar numDataArrayReads; 1232378SN/A Stats::Scalar numDataArrayWrites; 1242378SN/A Stats::Scalar numTagArrayReads; 1252378SN/A Stats::Scalar numTagArrayWrites; 1262378SN/A 1271885SN/A bool checkResourceAvailable(CacheResourceType res, Address addr); 1281885SN/A 1292901Ssaidi@eecs.umich.edu Stats::Scalar numTagArrayStalls; 1302901Ssaidi@eecs.umich.edu Stats::Scalar numDataArrayStalls; 1312424SN/A private: 1321885SN/A // convert a Address to its location in the cache 1331885SN/A Index addressToCacheSet(const Address& address) const; 1341885SN/A 1351885SN/A // Given a cache tag: returns the index of the tag in a set. 1361885SN/A // returns -1 if the tag is not found. 1372158SN/A int findTagInSet(Index line, const Address& tag) const; 1381885SN/A int findTagInSetIgnorePermissions(Index cacheSet, 1391885SN/A const Address& tag) const; 1401885SN/A 1411885SN/A // Private copy constructor and assignment operator 1421885SN/A CacheMemory(const CacheMemory& obj); 1431885SN/A CacheMemory& operator=(const CacheMemory& obj); 1442989Ssaidi@eecs.umich.edu 1451885SN/A private: 1461913SN/A const std::string m_cache_name; 1471885SN/A Cycles m_latency; 1481885SN/A 1491885SN/A // Data Members (m_prefix) 1501885SN/A bool m_is_instruction_only_cache; 1511885SN/A 1521885SN/A // The first index is the # of cache lines. 1531885SN/A // The second index is the the amount associativity. 1541885SN/A m5::hash_map<Address, int> m_tag_index; 1551885SN/A std::vector<std::vector<AbstractCacheEntry*> > m_cache; 1561885SN/A 1571885SN/A AbstractReplacementPolicy *m_replacementPolicy_ptr; 1582989Ssaidi@eecs.umich.edu 1591885SN/A CacheProfiler* m_profiler_ptr; 1601885SN/A 1611885SN/A BankedArray dataArray; 1621885SN/A BankedArray tagArray; 1632378SN/A 16477SN/A int m_cache_size; 1652378SN/A std::string m_policy; 1661070SN/A int m_cache_num_sets; 1671070SN/A int m_cache_num_set_bits; 1682158SN/A int m_cache_assoc; 1692378SN/A int m_start_index_bit; 1701070SN/A bool m_resource_stalls; 1711070SN/A}; 1721070SN/A 1731070SN/Astd::ostream& operator<<(std::ostream& out, const CacheMemory& obj); 1741070SN/A 1752521SN/A#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__ 1762902Ssaidi@eecs.umich.edu