CacheMemory.hh revision 11168
112854Sgabeblack@google.com/* 212854Sgabeblack@google.com * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 312854Sgabeblack@google.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 412854Sgabeblack@google.com * All rights reserved. 512854Sgabeblack@google.com * 612854Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 712854Sgabeblack@google.com * modification, are permitted provided that the following conditions are 812854Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 912854Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 1012854Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1112854Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1212854Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1312854Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1412854Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1512854Sgabeblack@google.com * this software without specific prior written permission. 1612854Sgabeblack@google.com * 1712854Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1812854Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1912854Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2012854Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2112854Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2212854Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2312854Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2412854Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2512854Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2612854Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2712854Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2812854Sgabeblack@google.com */ 2912854Sgabeblack@google.com 3012854Sgabeblack@google.com#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 3112854Sgabeblack@google.com#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 3212854Sgabeblack@google.com 3312854Sgabeblack@google.com#include <string> 3412854Sgabeblack@google.com#include <unordered_map> 3512854Sgabeblack@google.com#include <vector> 3612854Sgabeblack@google.com 3712854Sgabeblack@google.com#include "base/statistics.hh" 3812854Sgabeblack@google.com#include "mem/protocol/CacheRequestType.hh" 3912854Sgabeblack@google.com#include "mem/protocol/CacheResourceType.hh" 4012854Sgabeblack@google.com#include "mem/protocol/RubyRequest.hh" 4112854Sgabeblack@google.com#include "mem/ruby/common/DataBlock.hh" 4212854Sgabeblack@google.com#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 4312854Sgabeblack@google.com#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 4412854Sgabeblack@google.com#include "mem/ruby/structures/AbstractReplacementPolicy.hh" 4512854Sgabeblack@google.com#include "mem/ruby/structures/BankedArray.hh" 4612854Sgabeblack@google.com#include "mem/ruby/system/CacheRecorder.hh" 4712854Sgabeblack@google.com#include "params/RubyCache.hh" 4812854Sgabeblack@google.com#include "sim/sim_object.hh" 4912854Sgabeblack@google.com 5012854Sgabeblack@google.comclass CacheMemory : public SimObject 5112854Sgabeblack@google.com{ 5212854Sgabeblack@google.com public: 5312854Sgabeblack@google.com typedef RubyCacheParams Params; 5412854Sgabeblack@google.com CacheMemory(const Params *p); 5512854Sgabeblack@google.com ~CacheMemory(); 5612854Sgabeblack@google.com 5712854Sgabeblack@google.com void init(); 5812854Sgabeblack@google.com 5912854Sgabeblack@google.com // Public Methods 6012854Sgabeblack@google.com // perform a cache access and see if we hit or not. Return true on a hit. 6112854Sgabeblack@google.com bool tryCacheAccess(Addr address, RubyRequestType type, 6212854Sgabeblack@google.com DataBlock*& data_ptr); 6312854Sgabeblack@google.com 6412854Sgabeblack@google.com // similar to above, but doesn't require full access check 6512854Sgabeblack@google.com bool testCacheAccess(Addr address, RubyRequestType type, 6612854Sgabeblack@google.com DataBlock*& data_ptr); 6712854Sgabeblack@google.com 6812854Sgabeblack@google.com // tests to see if an address is present in the cache 6912854Sgabeblack@google.com bool isTagPresent(Addr address) const; 7012854Sgabeblack@google.com 7112854Sgabeblack@google.com // Returns true if there is: 7212854Sgabeblack@google.com // a) a tag match on this address or there is 7312854Sgabeblack@google.com // b) an unused line in the same cache "way" 7412854Sgabeblack@google.com bool cacheAvail(Addr address) const; 7512854Sgabeblack@google.com 7612854Sgabeblack@google.com // find an unused entry and sets the tag appropriate for the address 7712854Sgabeblack@google.com AbstractCacheEntry* allocate(Addr address, 7812854Sgabeblack@google.com AbstractCacheEntry* new_entry, bool touch); 7912854Sgabeblack@google.com AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry) 8012854Sgabeblack@google.com { 8112854Sgabeblack@google.com return allocate(address, new_entry, true); 8212854Sgabeblack@google.com } 8312854Sgabeblack@google.com void allocateVoid(Addr address, AbstractCacheEntry* new_entry) 8412854Sgabeblack@google.com { 8512854Sgabeblack@google.com allocate(address, new_entry, true); 8612854Sgabeblack@google.com } 87 88 // Explicitly free up this address 89 void deallocate(Addr address); 90 91 // Returns with the physical address of the conflicting cache line 92 Addr cacheProbe(Addr address) const; 93 94 // looks an address up in the cache 95 AbstractCacheEntry* lookup(Addr address); 96 const AbstractCacheEntry* lookup(Addr address) const; 97 98 Cycles getTagLatency() const { return tagArray.getLatency(); } 99 Cycles getDataLatency() const { return dataArray.getLatency(); } 100 101 bool isBlockInvalid(int64_t cache_set, int64_t loc); 102 bool isBlockNotBusy(int64_t cache_set, int64_t loc); 103 104 // Hook for checkpointing the contents of the cache 105 void recordCacheContents(int cntrl, CacheRecorder* tr) const; 106 107 // Set this address to most recently used 108 void setMRU(Addr address); 109 // Set this entry to most recently used 110 void setMRU(const AbstractCacheEntry *e); 111 112 // Functions for locking and unlocking cache lines corresponding to the 113 // provided address. These are required for supporting atomic memory 114 // accesses. These are to be used when only the address of the cache entry 115 // is available. In case the entry itself is available. use the functions 116 // provided by the AbstractCacheEntry class. 117 void setLocked (Addr addr, int context); 118 void clearLocked (Addr addr); 119 bool isLocked (Addr addr, int context); 120 121 // Print cache contents 122 void print(std::ostream& out) const; 123 void printData(std::ostream& out) const; 124 125 void regStats(); 126 bool checkResourceAvailable(CacheResourceType res, Addr addr); 127 void recordRequestType(CacheRequestType requestType, Addr addr); 128 129 public: 130 Stats::Scalar m_demand_hits; 131 Stats::Scalar m_demand_misses; 132 Stats::Formula m_demand_accesses; 133 134 Stats::Scalar m_sw_prefetches; 135 Stats::Scalar m_hw_prefetches; 136 Stats::Formula m_prefetches; 137 138 Stats::Vector m_accessModeType; 139 140 Stats::Scalar numDataArrayReads; 141 Stats::Scalar numDataArrayWrites; 142 Stats::Scalar numTagArrayReads; 143 Stats::Scalar numTagArrayWrites; 144 145 Stats::Scalar numTagArrayStalls; 146 Stats::Scalar numDataArrayStalls; 147 148 int getCacheSize() const { return m_cache_size; } 149 int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; } 150 Addr getAddressAtIdx(int idx) const; 151 152 private: 153 // convert a Address to its location in the cache 154 int64_t addressToCacheSet(Addr address) const; 155 156 // Given a cache tag: returns the index of the tag in a set. 157 // returns -1 if the tag is not found. 158 int findTagInSet(int64_t line, Addr tag) const; 159 int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const; 160 161 // Private copy constructor and assignment operator 162 CacheMemory(const CacheMemory& obj); 163 CacheMemory& operator=(const CacheMemory& obj); 164 165 private: 166 // Data Members (m_prefix) 167 bool m_is_instruction_only_cache; 168 169 // The first index is the # of cache lines. 170 // The second index is the the amount associativity. 171 std::unordered_map<Addr, int> m_tag_index; 172 std::vector<std::vector<AbstractCacheEntry*> > m_cache; 173 174 AbstractReplacementPolicy *m_replacementPolicy_ptr; 175 176 BankedArray dataArray; 177 BankedArray tagArray; 178 179 int m_cache_size; 180 int m_cache_num_sets; 181 int m_cache_num_set_bits; 182 int m_cache_assoc; 183 int m_start_index_bit; 184 bool m_resource_stalls; 185}; 186 187std::ostream& operator<<(std::ostream& out, const CacheMemory& obj); 188 189#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 190