CacheMemory.hh revision 11059
110448Snilay@cs.wisc.edu/* 210448Snilay@cs.wisc.edu * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 310448Snilay@cs.wisc.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 410448Snilay@cs.wisc.edu * All rights reserved. 510448Snilay@cs.wisc.edu * 610448Snilay@cs.wisc.edu * Redistribution and use in source and binary forms, with or without 710448Snilay@cs.wisc.edu * modification, are permitted provided that the following conditions are 810448Snilay@cs.wisc.edu * met: redistributions of source code must retain the above copyright 910448Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer; 1010448Snilay@cs.wisc.edu * redistributions in binary form must reproduce the above copyright 1110448Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer in the 1210448Snilay@cs.wisc.edu * documentation and/or other materials provided with the distribution; 1310448Snilay@cs.wisc.edu * neither the name of the copyright holders nor the names of its 1410448Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 1510448Snilay@cs.wisc.edu * this software without specific prior written permission. 1610448Snilay@cs.wisc.edu * 1710448Snilay@cs.wisc.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1810448Snilay@cs.wisc.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1910448Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2010448Snilay@cs.wisc.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2110448Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2210447Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2310447Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2410447Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2510447Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2610447Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2710447Snilay@cs.wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2810447Snilay@cs.wisc.edu */ 2910447Snilay@cs.wisc.edu 3010447Snilay@cs.wisc.edu#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 3110447Snilay@cs.wisc.edu#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 3210447Snilay@cs.wisc.edu 3310447Snilay@cs.wisc.edu#include <string> 3410447Snilay@cs.wisc.edu#include <vector> 3510447Snilay@cs.wisc.edu 3610447Snilay@cs.wisc.edu#include "base/hashmap.hh" 3710447Snilay@cs.wisc.edu#include "base/statistics.hh" 3810447Snilay@cs.wisc.edu#include "mem/protocol/CacheRequestType.hh" 3910447Snilay@cs.wisc.edu#include "mem/protocol/CacheResourceType.hh" 4010447Snilay@cs.wisc.edu#include "mem/protocol/RubyRequest.hh" 4110447Snilay@cs.wisc.edu#include "mem/ruby/common/DataBlock.hh" 4210447Snilay@cs.wisc.edu#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 4310447Snilay@cs.wisc.edu#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 4410447Snilay@cs.wisc.edu#include "mem/ruby/structures/AbstractReplacementPolicy.hh" 4510447Snilay@cs.wisc.edu#include "mem/ruby/structures/BankedArray.hh" 4610447Snilay@cs.wisc.edu#include "mem/ruby/system/CacheRecorder.hh" 4710447Snilay@cs.wisc.edu#include "params/RubyCache.hh" 4810447Snilay@cs.wisc.edu#include "sim/sim_object.hh" 4910447Snilay@cs.wisc.edu 5010447Snilay@cs.wisc.educlass CacheMemory : public SimObject 5110447Snilay@cs.wisc.edu{ 5210447Snilay@cs.wisc.edu public: 5310447Snilay@cs.wisc.edu typedef RubyCacheParams Params; 5410447Snilay@cs.wisc.edu CacheMemory(const Params *p); 5510447Snilay@cs.wisc.edu ~CacheMemory(); 5610447Snilay@cs.wisc.edu 5710447Snilay@cs.wisc.edu void init(); 5810447Snilay@cs.wisc.edu 5910447Snilay@cs.wisc.edu // Public Methods 6010447Snilay@cs.wisc.edu // perform a cache access and see if we hit or not. Return true on a hit. 6110447Snilay@cs.wisc.edu bool tryCacheAccess(Addr address, RubyRequestType type, 6210447Snilay@cs.wisc.edu DataBlock*& data_ptr); 6310447Snilay@cs.wisc.edu 6410447Snilay@cs.wisc.edu // similar to above, but doesn't require full access check 6510447Snilay@cs.wisc.edu bool testCacheAccess(Addr address, RubyRequestType type, 6610447Snilay@cs.wisc.edu DataBlock*& data_ptr); 6710447Snilay@cs.wisc.edu 6810447Snilay@cs.wisc.edu // tests to see if an address is present in the cache 6910447Snilay@cs.wisc.edu bool isTagPresent(Addr address) const; 7010447Snilay@cs.wisc.edu 7110447Snilay@cs.wisc.edu // Returns true if there is: 7210447Snilay@cs.wisc.edu // a) a tag match on this address or there is 7310447Snilay@cs.wisc.edu // b) an unused line in the same cache "way" 7410447Snilay@cs.wisc.edu bool cacheAvail(Addr address) const; 7510447Snilay@cs.wisc.edu 7610447Snilay@cs.wisc.edu // find an unused entry and sets the tag appropriate for the address 7710447Snilay@cs.wisc.edu AbstractCacheEntry* allocate(Addr address, 7810447Snilay@cs.wisc.edu AbstractCacheEntry* new_entry, bool touch); 7910447Snilay@cs.wisc.edu AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry) 8010447Snilay@cs.wisc.edu { 8110447Snilay@cs.wisc.edu return allocate(address, new_entry, true); 8210447Snilay@cs.wisc.edu } 8310447Snilay@cs.wisc.edu void allocateVoid(Addr address, AbstractCacheEntry* new_entry) 8410447Snilay@cs.wisc.edu { 8510447Snilay@cs.wisc.edu allocate(address, new_entry, true); 8610447Snilay@cs.wisc.edu } 8710447Snilay@cs.wisc.edu 8810447Snilay@cs.wisc.edu // Explicitly free up this address 8910447Snilay@cs.wisc.edu void deallocate(Addr address); 9010447Snilay@cs.wisc.edu 9110447Snilay@cs.wisc.edu // Returns with the physical address of the conflicting cache line 9210447Snilay@cs.wisc.edu Addr cacheProbe(Addr address) const; 9310447Snilay@cs.wisc.edu 9410447Snilay@cs.wisc.edu // looks an address up in the cache 9510447Snilay@cs.wisc.edu AbstractCacheEntry* lookup(Addr address); 9610447Snilay@cs.wisc.edu const AbstractCacheEntry* lookup(Addr address) const; 9710447Snilay@cs.wisc.edu 9810447Snilay@cs.wisc.edu Cycles getTagLatency() const { return tagArray.getLatency(); } 9910447Snilay@cs.wisc.edu Cycles getDataLatency() const { return dataArray.getLatency(); } 10010447Snilay@cs.wisc.edu 10110447Snilay@cs.wisc.edu bool isBlockInvalid(int64 cache_set, int64 loc); 10210447Snilay@cs.wisc.edu bool isBlockNotBusy(int64 cache_set, int64 loc); 10310447Snilay@cs.wisc.edu 10410447Snilay@cs.wisc.edu // Hook for checkpointing the contents of the cache 10510447Snilay@cs.wisc.edu void recordCacheContents(int cntrl, CacheRecorder* tr) const; 10610447Snilay@cs.wisc.edu 10710447Snilay@cs.wisc.edu // Set this address to most recently used 108 void setMRU(Addr address); 109 110 // Functions for locking and unlocking cache lines corresponding to the 111 // provided address. These are required for supporting atomic memory 112 // accesses. These are to be used when only the address of the cache entry 113 // is available. In case the entry itself is available. use the functions 114 // provided by the AbstractCacheEntry class. 115 void setLocked (Addr addr, int context); 116 void clearLocked (Addr addr); 117 bool isLocked (Addr addr, int context); 118 119 // Print cache contents 120 void print(std::ostream& out) const; 121 void printData(std::ostream& out) const; 122 123 void regStats(); 124 bool checkResourceAvailable(CacheResourceType res, Addr addr); 125 void recordRequestType(CacheRequestType requestType, Addr addr); 126 127 public: 128 Stats::Scalar m_demand_hits; 129 Stats::Scalar m_demand_misses; 130 Stats::Formula m_demand_accesses; 131 132 Stats::Scalar m_sw_prefetches; 133 Stats::Scalar m_hw_prefetches; 134 Stats::Formula m_prefetches; 135 136 Stats::Vector m_accessModeType; 137 138 Stats::Scalar numDataArrayReads; 139 Stats::Scalar numDataArrayWrites; 140 Stats::Scalar numTagArrayReads; 141 Stats::Scalar numTagArrayWrites; 142 143 Stats::Scalar numTagArrayStalls; 144 Stats::Scalar numDataArrayStalls; 145 146 int getCacheSize() const { return m_cache_size; } 147 int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; } 148 Addr getAddressAtIdx(int idx) const; 149 150 private: 151 // convert a Address to its location in the cache 152 int64 addressToCacheSet(Addr address) const; 153 154 // Given a cache tag: returns the index of the tag in a set. 155 // returns -1 if the tag is not found. 156 int findTagInSet(int64 line, Addr tag) const; 157 int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const; 158 159 // Private copy constructor and assignment operator 160 CacheMemory(const CacheMemory& obj); 161 CacheMemory& operator=(const CacheMemory& obj); 162 163 private: 164 // Data Members (m_prefix) 165 bool m_is_instruction_only_cache; 166 167 // The first index is the # of cache lines. 168 // The second index is the the amount associativity. 169 m5::hash_map<Addr, int> m_tag_index; 170 std::vector<std::vector<AbstractCacheEntry*> > m_cache; 171 172 AbstractReplacementPolicy *m_replacementPolicy_ptr; 173 174 BankedArray dataArray; 175 BankedArray tagArray; 176 177 int m_cache_size; 178 int m_cache_num_sets; 179 int m_cache_num_set_bits; 180 int m_cache_assoc; 181 int m_start_index_bit; 182 bool m_resource_stalls; 183}; 184 185std::ostream& operator<<(std::ostream& out, const CacheMemory& obj); 186 187#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 188