CacheMemory.hh revision 11049
16145SN/A/* 28683SN/A * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 310973Sdavid.hashe@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 46145SN/A * All rights reserved. 56145SN/A * 66145SN/A * Redistribution and use in source and binary forms, with or without 76145SN/A * modification, are permitted provided that the following conditions are 86145SN/A * met: redistributions of source code must retain the above copyright 96145SN/A * notice, this list of conditions and the following disclaimer; 106145SN/A * redistributions in binary form must reproduce the above copyright 116145SN/A * notice, this list of conditions and the following disclaimer in the 126145SN/A * documentation and/or other materials provided with the distribution; 136145SN/A * neither the name of the copyright holders nor the names of its 146145SN/A * contributors may be used to endorse or promote products derived from 156145SN/A * this software without specific prior written permission. 166145SN/A * 176145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286145SN/A */ 296145SN/A 3010441Snilay@cs.wisc.edu#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 3110441Snilay@cs.wisc.edu#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 326145SN/A 337055SN/A#include <string> 346145SN/A#include <vector> 356145SN/A 367039SN/A#include "base/hashmap.hh" 379104SN/A#include "base/statistics.hh" 3810301Snilay@cs.wisc.edu#include "mem/protocol/CacheRequestType.hh" 399105SN/A#include "mem/protocol/CacheResourceType.hh" 408174SN/A#include "mem/protocol/RubyRequest.hh" 417039SN/A#include "mem/ruby/common/DataBlock.hh" 427039SN/A#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 437039SN/A#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 4410970Sdavid.hashe@amd.com#include "mem/ruby/structures/AbstractReplacementPolicy.hh" 4510301Snilay@cs.wisc.edu#include "mem/ruby/structures/BankedArray.hh" 4610301Snilay@cs.wisc.edu#include "mem/ruby/system/CacheRecorder.hh" 477039SN/A#include "params/RubyCache.hh" 487039SN/A#include "sim/sim_object.hh" 496145SN/A 507039SN/Aclass CacheMemory : public SimObject 517039SN/A{ 527039SN/A public: 536876SN/A typedef RubyCacheParams Params; 547039SN/A CacheMemory(const Params *p); 557039SN/A ~CacheMemory(); 566145SN/A 577039SN/A void init(); 586145SN/A 5911049Snilay@cs.wisc.edu // Public Methods 6011049Snilay@cs.wisc.edu // perform a cache access and see if we hit or not. Return true on a hit. 6111049Snilay@cs.wisc.edu bool tryCacheAccess(Addr address, RubyRequestType type, 6211049Snilay@cs.wisc.edu DataBlock*& data_ptr); 6311049Snilay@cs.wisc.edu 6411049Snilay@cs.wisc.edu // similar to above, but doesn't require full access check 6511049Snilay@cs.wisc.edu bool testCacheAccess(Addr address, RubyRequestType type, 6611049Snilay@cs.wisc.edu DataBlock*& data_ptr); 6711049Snilay@cs.wisc.edu 687039SN/A // tests to see if an address is present in the cache 6911025Snilay@cs.wisc.edu bool isTagPresent(Addr address) const; 706145SN/A 717039SN/A // Returns true if there is: 727039SN/A // a) a tag match on this address or there is 737039SN/A // b) an unused line in the same cache "way" 7411025Snilay@cs.wisc.edu bool cacheAvail(Addr address) const; 756145SN/A 767039SN/A // find an unused entry and sets the tag appropriate for the address 7711025Snilay@cs.wisc.edu AbstractCacheEntry* allocate(Addr address, 7810974Sdavid.hashe@amd.com AbstractCacheEntry* new_entry, bool touch); 7911025Snilay@cs.wisc.edu AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry) 8010974Sdavid.hashe@amd.com { 8110974Sdavid.hashe@amd.com return allocate(address, new_entry, true); 8210974Sdavid.hashe@amd.com } 8311025Snilay@cs.wisc.edu void allocateVoid(Addr address, AbstractCacheEntry* new_entry) 848193SN/A { 8510974Sdavid.hashe@amd.com allocate(address, new_entry, true); 868193SN/A } 876145SN/A 887039SN/A // Explicitly free up this address 8911025Snilay@cs.wisc.edu void deallocate(Addr address); 906145SN/A 917039SN/A // Returns with the physical address of the conflicting cache line 9211025Snilay@cs.wisc.edu Addr cacheProbe(Addr address) const; 936145SN/A 947039SN/A // looks an address up in the cache 9511025Snilay@cs.wisc.edu AbstractCacheEntry* lookup(Addr address); 9611025Snilay@cs.wisc.edu const AbstractCacheEntry* lookup(Addr address) const; 976145SN/A 9810969Sdavid.hashe@amd.com Cycles getTagLatency() const { return tagArray.getLatency(); } 9910969Sdavid.hashe@amd.com Cycles getDataLatency() const { return dataArray.getLatency(); } 10010969Sdavid.hashe@amd.com 10111049Snilay@cs.wisc.edu bool isBlockInvalid(int64 cache_set, int64 loc); 10211049Snilay@cs.wisc.edu bool isBlockNotBusy(int64 cache_set, int64 loc); 1036285SN/A 1047039SN/A // Hook for checkpointing the contents of the cache 1058683SN/A void recordCacheContents(int cntrl, CacheRecorder* tr) const; 1066145SN/A 1077039SN/A // Set this address to most recently used 10811025Snilay@cs.wisc.edu void setMRU(Addr address); 1096145SN/A 11011025Snilay@cs.wisc.edu void setLocked (Addr addr, int context); 11111025Snilay@cs.wisc.edu void clearLocked (Addr addr); 11211025Snilay@cs.wisc.edu bool isLocked (Addr addr, int context); 1139692SN/A 1147039SN/A // Print cache contents 1157055SN/A void print(std::ostream& out) const; 1167055SN/A void printData(std::ostream& out) const; 1176145SN/A 1189692SN/A void regStats(); 11911025Snilay@cs.wisc.edu bool checkResourceAvailable(CacheResourceType res, Addr addr); 12011025Snilay@cs.wisc.edu void recordRequestType(CacheRequestType requestType, Addr addr); 1216374SN/A 1229692SN/A public: 1239692SN/A Stats::Scalar m_demand_hits; 1249692SN/A Stats::Scalar m_demand_misses; 1259692SN/A Stats::Formula m_demand_accesses; 1269692SN/A 1279692SN/A Stats::Scalar m_sw_prefetches; 1289692SN/A Stats::Scalar m_hw_prefetches; 1299692SN/A Stats::Formula m_prefetches; 1309692SN/A 1319692SN/A Stats::Vector m_accessModeType; 1329104SN/A 1339104SN/A Stats::Scalar numDataArrayReads; 1349104SN/A Stats::Scalar numDataArrayWrites; 1359104SN/A Stats::Scalar numTagArrayReads; 1369104SN/A Stats::Scalar numTagArrayWrites; 1379104SN/A 1389105SN/A Stats::Scalar numTagArrayStalls; 1399105SN/A Stats::Scalar numDataArrayStalls; 1409692SN/A 14110973Sdavid.hashe@amd.com int getCacheSize() const { return m_cache_size; } 14210973Sdavid.hashe@amd.com int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; } 14311025Snilay@cs.wisc.edu Addr getAddressAtIdx(int idx) const; 14410973Sdavid.hashe@amd.com 1457039SN/A private: 1467039SN/A // convert a Address to its location in the cache 14711049Snilay@cs.wisc.edu int64 addressToCacheSet(Addr address) const; 1486145SN/A 1497039SN/A // Given a cache tag: returns the index of the tag in a set. 1507039SN/A // returns -1 if the tag is not found. 15111049Snilay@cs.wisc.edu int findTagInSet(int64 line, Addr tag) const; 15211049Snilay@cs.wisc.edu int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const; 1536145SN/A 1547039SN/A // Private copy constructor and assignment operator 1557039SN/A CacheMemory(const CacheMemory& obj); 1567039SN/A CacheMemory& operator=(const CacheMemory& obj); 1576145SN/A 1587039SN/A private: 1597039SN/A // Data Members (m_prefix) 1607039SN/A bool m_is_instruction_only_cache; 1616285SN/A 1627039SN/A // The first index is the # of cache lines. 1637039SN/A // The second index is the the amount associativity. 16411025Snilay@cs.wisc.edu m5::hash_map<Addr, int> m_tag_index; 1657454SN/A std::vector<std::vector<AbstractCacheEntry*> > m_cache; 1666145SN/A 1677039SN/A AbstractReplacementPolicy *m_replacementPolicy_ptr; 1686145SN/A 1699105SN/A BankedArray dataArray; 1709105SN/A BankedArray tagArray; 1719105SN/A 1727039SN/A int m_cache_size; 1737039SN/A int m_cache_num_sets; 1747039SN/A int m_cache_num_set_bits; 1757039SN/A int m_cache_assoc; 1767564SN/A int m_start_index_bit; 1779105SN/A bool m_resource_stalls; 1786145SN/A}; 1796145SN/A 1809554SN/Astd::ostream& operator<<(std::ostream& out, const CacheMemory& obj); 1819554SN/A 18210441Snilay@cs.wisc.edu#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 183