CacheMemory.cc revision 11087:3c4bda5a2f66
1/* 2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include "base/intmath.hh" 31#include "debug/RubyCache.hh" 32#include "debug/RubyCacheTrace.hh" 33#include "debug/RubyResourceStalls.hh" 34#include "debug/RubyStats.hh" 35#include "mem/protocol/AccessPermission.hh" 36#include "mem/ruby/structures/CacheMemory.hh" 37#include "mem/ruby/system/System.hh" 38 39using namespace std; 40 41ostream& 42operator<<(ostream& out, const CacheMemory& obj) 43{ 44 obj.print(out); 45 out << flush; 46 return out; 47} 48 49CacheMemory * 50RubyCacheParams::create() 51{ 52 return new CacheMemory(this); 53} 54 55CacheMemory::CacheMemory(const Params *p) 56 : SimObject(p), 57 dataArray(p->dataArrayBanks, p->dataAccessLatency, 58 p->start_index_bit, p->ruby_system), 59 tagArray(p->tagArrayBanks, p->tagAccessLatency, 60 p->start_index_bit, p->ruby_system) 61{ 62 m_cache_size = p->size; 63 m_cache_assoc = p->assoc; 64 m_replacementPolicy_ptr = p->replacement_policy; 65 m_replacementPolicy_ptr->setCache(this); 66 m_start_index_bit = p->start_index_bit; 67 m_is_instruction_only_cache = p->is_icache; 68 m_resource_stalls = p->resourceStalls; 69} 70 71void 72CacheMemory::init() 73{ 74 m_cache_num_sets = (m_cache_size / m_cache_assoc) / 75 RubySystem::getBlockSizeBytes(); 76 assert(m_cache_num_sets > 1); 77 m_cache_num_set_bits = floorLog2(m_cache_num_sets); 78 assert(m_cache_num_set_bits > 0); 79 80 m_cache.resize(m_cache_num_sets); 81 for (int i = 0; i < m_cache_num_sets; i++) { 82 m_cache[i].resize(m_cache_assoc); 83 for (int j = 0; j < m_cache_assoc; j++) { 84 m_cache[i][j] = NULL; 85 } 86 } 87} 88 89CacheMemory::~CacheMemory() 90{ 91 if (m_replacementPolicy_ptr != NULL) 92 delete m_replacementPolicy_ptr; 93 for (int i = 0; i < m_cache_num_sets; i++) { 94 for (int j = 0; j < m_cache_assoc; j++) { 95 delete m_cache[i][j]; 96 } 97 } 98} 99 100// convert a Address to its location in the cache 101int64_t 102CacheMemory::addressToCacheSet(Addr address) const 103{ 104 assert(address == makeLineAddress(address)); 105 return bitSelect(address, m_start_index_bit, 106 m_start_index_bit + m_cache_num_set_bits - 1); 107} 108 109// Given a cache index: returns the index of the tag in a set. 110// returns -1 if the tag is not found. 111int 112CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const 113{ 114 assert(tag == makeLineAddress(tag)); 115 // search the set for the tags 116 m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); 117 if (it != m_tag_index.end()) 118 if (m_cache[cacheSet][it->second]->m_Permission != 119 AccessPermission_NotPresent) 120 return it->second; 121 return -1; // Not found 122} 123 124// Given a cache index: returns the index of the tag in a set. 125// returns -1 if the tag is not found. 126int 127CacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet, 128 Addr tag) const 129{ 130 assert(tag == makeLineAddress(tag)); 131 // search the set for the tags 132 m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); 133 if (it != m_tag_index.end()) 134 return it->second; 135 return -1; // Not found 136} 137 138// Given an unique cache block identifier (idx): return the valid address 139// stored by the cache block. If the block is invalid/notpresent, the 140// function returns the 0 address 141Addr 142CacheMemory::getAddressAtIdx(int idx) const 143{ 144 Addr tmp(0); 145 146 int set = idx / m_cache_assoc; 147 assert(set < m_cache_num_sets); 148 149 int way = idx - set * m_cache_assoc; 150 assert (way < m_cache_assoc); 151 152 AbstractCacheEntry* entry = m_cache[set][way]; 153 if (entry == NULL || 154 entry->m_Permission == AccessPermission_Invalid || 155 entry->m_Permission == AccessPermission_NotPresent) { 156 return tmp; 157 } 158 return entry->m_Address; 159} 160 161bool 162CacheMemory::tryCacheAccess(Addr address, RubyRequestType type, 163 DataBlock*& data_ptr) 164{ 165 assert(address == makeLineAddress(address)); 166 DPRINTF(RubyCache, "address: %s\n", address); 167 int64_t cacheSet = addressToCacheSet(address); 168 int loc = findTagInSet(cacheSet, address); 169 if (loc != -1) { 170 // Do we even have a tag match? 171 AbstractCacheEntry* entry = m_cache[cacheSet][loc]; 172 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 173 data_ptr = &(entry->getDataBlk()); 174 175 if (entry->m_Permission == AccessPermission_Read_Write) { 176 return true; 177 } 178 if ((entry->m_Permission == AccessPermission_Read_Only) && 179 (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) { 180 return true; 181 } 182 // The line must not be accessible 183 } 184 data_ptr = NULL; 185 return false; 186} 187 188bool 189CacheMemory::testCacheAccess(Addr address, RubyRequestType type, 190 DataBlock*& data_ptr) 191{ 192 assert(address == makeLineAddress(address)); 193 DPRINTF(RubyCache, "address: %s\n", address); 194 int64_t cacheSet = addressToCacheSet(address); 195 int loc = findTagInSet(cacheSet, address); 196 197 if (loc != -1) { 198 // Do we even have a tag match? 199 AbstractCacheEntry* entry = m_cache[cacheSet][loc]; 200 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 201 data_ptr = &(entry->getDataBlk()); 202 203 return m_cache[cacheSet][loc]->m_Permission != 204 AccessPermission_NotPresent; 205 } 206 207 data_ptr = NULL; 208 return false; 209} 210 211// tests to see if an address is present in the cache 212bool 213CacheMemory::isTagPresent(Addr address) const 214{ 215 assert(address == makeLineAddress(address)); 216 int64_t cacheSet = addressToCacheSet(address); 217 int loc = findTagInSet(cacheSet, address); 218 219 if (loc == -1) { 220 // We didn't find the tag 221 DPRINTF(RubyCache, "No tag match for address: %s\n", address); 222 return false; 223 } 224 DPRINTF(RubyCache, "address: %s found\n", address); 225 return true; 226} 227 228// Returns true if there is: 229// a) a tag match on this address or there is 230// b) an unused line in the same cache "way" 231bool 232CacheMemory::cacheAvail(Addr address) const 233{ 234 assert(address == makeLineAddress(address)); 235 236 int64_t cacheSet = addressToCacheSet(address); 237 238 for (int i = 0; i < m_cache_assoc; i++) { 239 AbstractCacheEntry* entry = m_cache[cacheSet][i]; 240 if (entry != NULL) { 241 if (entry->m_Address == address || 242 entry->m_Permission == AccessPermission_NotPresent) { 243 // Already in the cache or we found an empty entry 244 return true; 245 } 246 } else { 247 return true; 248 } 249 } 250 return false; 251} 252 253AbstractCacheEntry* 254CacheMemory::allocate(Addr address, AbstractCacheEntry *entry, bool touch) 255{ 256 assert(address == makeLineAddress(address)); 257 assert(!isTagPresent(address)); 258 assert(cacheAvail(address)); 259 DPRINTF(RubyCache, "address: %s\n", address); 260 261 // Find the first open slot 262 int64_t cacheSet = addressToCacheSet(address); 263 std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet]; 264 for (int i = 0; i < m_cache_assoc; i++) { 265 if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) { 266 set[i] = entry; // Init entry 267 set[i]->m_Address = address; 268 set[i]->m_Permission = AccessPermission_Invalid; 269 DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n", 270 address); 271 set[i]->m_locked = -1; 272 m_tag_index[address] = i; 273 entry->setSetIndex(cacheSet); 274 entry->setWayIndex(i); 275 276 if (touch) { 277 m_replacementPolicy_ptr->touch(cacheSet, i, curTick()); 278 } 279 280 return entry; 281 } 282 } 283 panic("Allocate didn't find an available entry"); 284} 285 286void 287CacheMemory::deallocate(Addr address) 288{ 289 assert(address == makeLineAddress(address)); 290 assert(isTagPresent(address)); 291 DPRINTF(RubyCache, "address: %s\n", address); 292 int64_t cacheSet = addressToCacheSet(address); 293 int loc = findTagInSet(cacheSet, address); 294 if (loc != -1) { 295 delete m_cache[cacheSet][loc]; 296 m_cache[cacheSet][loc] = NULL; 297 m_tag_index.erase(address); 298 } 299} 300 301// Returns with the physical address of the conflicting cache line 302Addr 303CacheMemory::cacheProbe(Addr address) const 304{ 305 assert(address == makeLineAddress(address)); 306 assert(!cacheAvail(address)); 307 308 int64_t cacheSet = addressToCacheSet(address); 309 return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]-> 310 m_Address; 311} 312 313// looks an address up in the cache 314AbstractCacheEntry* 315CacheMemory::lookup(Addr address) 316{ 317 assert(address == makeLineAddress(address)); 318 int64_t cacheSet = addressToCacheSet(address); 319 int loc = findTagInSet(cacheSet, address); 320 if(loc == -1) return NULL; 321 return m_cache[cacheSet][loc]; 322} 323 324// looks an address up in the cache 325const AbstractCacheEntry* 326CacheMemory::lookup(Addr address) const 327{ 328 assert(address == makeLineAddress(address)); 329 int64_t cacheSet = addressToCacheSet(address); 330 int loc = findTagInSet(cacheSet, address); 331 if(loc == -1) return NULL; 332 return m_cache[cacheSet][loc]; 333} 334 335// Sets the most recently used bit for a cache block 336void 337CacheMemory::setMRU(Addr address) 338{ 339 int64_t cacheSet = addressToCacheSet(address); 340 int loc = findTagInSet(cacheSet, address); 341 342 if(loc != -1) 343 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 344} 345 346void 347CacheMemory::setMRU(const AbstractCacheEntry *e) 348{ 349 uint32_t cacheSet = e->getSetIndex(); 350 uint32_t loc = e->getWayIndex(); 351 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 352} 353 354void 355CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const 356{ 357 uint64_t warmedUpBlocks = 0; 358 uint64_t totalBlocks M5_VAR_USED = (uint64_t)m_cache_num_sets * 359 (uint64_t)m_cache_assoc; 360 361 for (int i = 0; i < m_cache_num_sets; i++) { 362 for (int j = 0; j < m_cache_assoc; j++) { 363 if (m_cache[i][j] != NULL) { 364 AccessPermission perm = m_cache[i][j]->m_Permission; 365 RubyRequestType request_type = RubyRequestType_NULL; 366 if (perm == AccessPermission_Read_Only) { 367 if (m_is_instruction_only_cache) { 368 request_type = RubyRequestType_IFETCH; 369 } else { 370 request_type = RubyRequestType_LD; 371 } 372 } else if (perm == AccessPermission_Read_Write) { 373 request_type = RubyRequestType_ST; 374 } 375 376 if (request_type != RubyRequestType_NULL) { 377 tr->addRecord(cntrl, m_cache[i][j]->m_Address, 378 0, request_type, 379 m_replacementPolicy_ptr->getLastAccess(i, j), 380 m_cache[i][j]->getDataBlk()); 381 warmedUpBlocks++; 382 } 383 } 384 } 385 } 386 387 DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks" 388 "recorded %.2f%% \n", name().c_str(), warmedUpBlocks, 389 totalBlocks, (float(warmedUpBlocks) / float(totalBlocks)) * 100.0); 390} 391 392void 393CacheMemory::print(ostream& out) const 394{ 395 out << "Cache dump: " << name() << endl; 396 for (int i = 0; i < m_cache_num_sets; i++) { 397 for (int j = 0; j < m_cache_assoc; j++) { 398 if (m_cache[i][j] != NULL) { 399 out << " Index: " << i 400 << " way: " << j 401 << " entry: " << *m_cache[i][j] << endl; 402 } else { 403 out << " Index: " << i 404 << " way: " << j 405 << " entry: NULL" << endl; 406 } 407 } 408 } 409} 410 411void 412CacheMemory::printData(ostream& out) const 413{ 414 out << "printData() not supported" << endl; 415} 416 417void 418CacheMemory::setLocked(Addr address, int context) 419{ 420 DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context); 421 assert(address == makeLineAddress(address)); 422 int64_t cacheSet = addressToCacheSet(address); 423 int loc = findTagInSet(cacheSet, address); 424 assert(loc != -1); 425 m_cache[cacheSet][loc]->setLocked(context); 426} 427 428void 429CacheMemory::clearLocked(Addr address) 430{ 431 DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address); 432 assert(address == makeLineAddress(address)); 433 int64_t cacheSet = addressToCacheSet(address); 434 int loc = findTagInSet(cacheSet, address); 435 assert(loc != -1); 436 m_cache[cacheSet][loc]->clearLocked(); 437} 438 439bool 440CacheMemory::isLocked(Addr address, int context) 441{ 442 assert(address == makeLineAddress(address)); 443 int64_t cacheSet = addressToCacheSet(address); 444 int loc = findTagInSet(cacheSet, address); 445 assert(loc != -1); 446 DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n", 447 address, m_cache[cacheSet][loc]->m_locked, context); 448 return m_cache[cacheSet][loc]->isLocked(context); 449} 450 451void 452CacheMemory::regStats() 453{ 454 m_demand_hits 455 .name(name() + ".demand_hits") 456 .desc("Number of cache demand hits") 457 ; 458 459 m_demand_misses 460 .name(name() + ".demand_misses") 461 .desc("Number of cache demand misses") 462 ; 463 464 m_demand_accesses 465 .name(name() + ".demand_accesses") 466 .desc("Number of cache demand accesses") 467 ; 468 469 m_demand_accesses = m_demand_hits + m_demand_misses; 470 471 m_sw_prefetches 472 .name(name() + ".total_sw_prefetches") 473 .desc("Number of software prefetches") 474 .flags(Stats::nozero) 475 ; 476 477 m_hw_prefetches 478 .name(name() + ".total_hw_prefetches") 479 .desc("Number of hardware prefetches") 480 .flags(Stats::nozero) 481 ; 482 483 m_prefetches 484 .name(name() + ".total_prefetches") 485 .desc("Number of prefetches") 486 .flags(Stats::nozero) 487 ; 488 489 m_prefetches = m_sw_prefetches + m_hw_prefetches; 490 491 m_accessModeType 492 .init(RubyRequestType_NUM) 493 .name(name() + ".access_mode") 494 .flags(Stats::pdf | Stats::total) 495 ; 496 for (int i = 0; i < RubyAccessMode_NUM; i++) { 497 m_accessModeType 498 .subname(i, RubyAccessMode_to_string(RubyAccessMode(i))) 499 .flags(Stats::nozero) 500 ; 501 } 502 503 numDataArrayReads 504 .name(name() + ".num_data_array_reads") 505 .desc("number of data array reads") 506 .flags(Stats::nozero) 507 ; 508 509 numDataArrayWrites 510 .name(name() + ".num_data_array_writes") 511 .desc("number of data array writes") 512 .flags(Stats::nozero) 513 ; 514 515 numTagArrayReads 516 .name(name() + ".num_tag_array_reads") 517 .desc("number of tag array reads") 518 .flags(Stats::nozero) 519 ; 520 521 numTagArrayWrites 522 .name(name() + ".num_tag_array_writes") 523 .desc("number of tag array writes") 524 .flags(Stats::nozero) 525 ; 526 527 numTagArrayStalls 528 .name(name() + ".num_tag_array_stalls") 529 .desc("number of stalls caused by tag array") 530 .flags(Stats::nozero) 531 ; 532 533 numDataArrayStalls 534 .name(name() + ".num_data_array_stalls") 535 .desc("number of stalls caused by data array") 536 .flags(Stats::nozero) 537 ; 538} 539 540// assumption: SLICC generated files will only call this function 541// once **all** resources are granted 542void 543CacheMemory::recordRequestType(CacheRequestType requestType, Addr addr) 544{ 545 DPRINTF(RubyStats, "Recorded statistic: %s\n", 546 CacheRequestType_to_string(requestType)); 547 switch(requestType) { 548 case CacheRequestType_DataArrayRead: 549 if (m_resource_stalls) 550 dataArray.reserve(addressToCacheSet(addr)); 551 numDataArrayReads++; 552 return; 553 case CacheRequestType_DataArrayWrite: 554 if (m_resource_stalls) 555 dataArray.reserve(addressToCacheSet(addr)); 556 numDataArrayWrites++; 557 return; 558 case CacheRequestType_TagArrayRead: 559 if (m_resource_stalls) 560 tagArray.reserve(addressToCacheSet(addr)); 561 numTagArrayReads++; 562 return; 563 case CacheRequestType_TagArrayWrite: 564 if (m_resource_stalls) 565 tagArray.reserve(addressToCacheSet(addr)); 566 numTagArrayWrites++; 567 return; 568 default: 569 warn("CacheMemory access_type not found: %s", 570 CacheRequestType_to_string(requestType)); 571 } 572} 573 574bool 575CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr) 576{ 577 if (!m_resource_stalls) { 578 return true; 579 } 580 581 if (res == CacheResourceType_TagArray) { 582 if (tagArray.tryAccess(addressToCacheSet(addr))) return true; 583 else { 584 DPRINTF(RubyResourceStalls, 585 "Tag array stall on addr %s in set %d\n", 586 addr, addressToCacheSet(addr)); 587 numTagArrayStalls++; 588 return false; 589 } 590 } else if (res == CacheResourceType_DataArray) { 591 if (dataArray.tryAccess(addressToCacheSet(addr))) return true; 592 else { 593 DPRINTF(RubyResourceStalls, 594 "Data array stall on addr %s in set %d\n", 595 addr, addressToCacheSet(addr)); 596 numDataArrayStalls++; 597 return false; 598 } 599 } else { 600 assert(false); 601 return true; 602 } 603} 604 605bool 606CacheMemory::isBlockInvalid(int64_t cache_set, int64_t loc) 607{ 608 return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid); 609} 610 611bool 612CacheMemory::isBlockNotBusy(int64_t cache_set, int64_t loc) 613{ 614 return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy); 615} 616