CacheMemory.cc revision 11061:25b53a7195f7 
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "base/intmath.hh"
31#include "debug/RubyCache.hh"
32#include "debug/RubyCacheTrace.hh"
33#include "debug/RubyResourceStalls.hh"
34#include "debug/RubyStats.hh"
35#include "mem/protocol/AccessPermission.hh"
36#include "mem/ruby/structures/CacheMemory.hh"
37#include "mem/ruby/system/System.hh"
38
39using namespace std;
40
41ostream&
42operator<<(ostream& out, const CacheMemory& obj)
43{
44    obj.print(out);
45    out << flush;
46    return out;
47}
48
49CacheMemory *
50RubyCacheParams::create()
51{
52    return new CacheMemory(this);
53}
54
55CacheMemory::CacheMemory(const Params *p)
56    : SimObject(p),
57    dataArray(p->dataArrayBanks, p->dataAccessLatency,
58              p->start_index_bit, p->ruby_system),
59    tagArray(p->tagArrayBanks, p->tagAccessLatency,
60             p->start_index_bit, p->ruby_system)
61{
62    m_cache_size = p->size;
63    m_cache_assoc = p->assoc;
64    m_replacementPolicy_ptr = p->replacement_policy;
65    m_replacementPolicy_ptr->setCache(this);
66    m_start_index_bit = p->start_index_bit;
67    m_is_instruction_only_cache = p->is_icache;
68    m_resource_stalls = p->resourceStalls;
69}
70
71void
72CacheMemory::init()
73{
74    m_cache_num_sets = (m_cache_size / m_cache_assoc) /
75        RubySystem::getBlockSizeBytes();
76    assert(m_cache_num_sets > 1);
77    m_cache_num_set_bits = floorLog2(m_cache_num_sets);
78    assert(m_cache_num_set_bits > 0);
79
80    m_cache.resize(m_cache_num_sets);
81    for (int i = 0; i < m_cache_num_sets; i++) {
82        m_cache[i].resize(m_cache_assoc);
83        for (int j = 0; j < m_cache_assoc; j++) {
84            m_cache[i][j] = NULL;
85        }
86    }
87}
88
89CacheMemory::~CacheMemory()
90{
91    if (m_replacementPolicy_ptr != NULL)
92        delete m_replacementPolicy_ptr;
93    for (int i = 0; i < m_cache_num_sets; i++) {
94        for (int j = 0; j < m_cache_assoc; j++) {
95            delete m_cache[i][j];
96        }
97    }
98}
99
100// convert a Address to its location in the cache
101int64_t
102CacheMemory::addressToCacheSet(Addr address) const
103{
104    assert(address == makeLineAddress(address));
105    return bitSelect(address, m_start_index_bit,
106                     m_start_index_bit + m_cache_num_set_bits - 1);
107}
108
109// Given a cache index: returns the index of the tag in a set.
110// returns -1 if the tag is not found.
111int
112CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const
113{
114    assert(tag == makeLineAddress(tag));
115    // search the set for the tags
116    m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
117    if (it != m_tag_index.end())
118        if (m_cache[cacheSet][it->second]->m_Permission !=
119            AccessPermission_NotPresent)
120            return it->second;
121    return -1; // Not found
122}
123
124// Given a cache index: returns the index of the tag in a set.
125// returns -1 if the tag is not found.
126int
127CacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet,
128                                           Addr tag) const
129{
130    assert(tag == makeLineAddress(tag));
131    // search the set for the tags
132    m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
133    if (it != m_tag_index.end())
134        return it->second;
135    return -1; // Not found
136}
137
138// Given an unique cache block identifier (idx): return the valid address
139// stored by the cache block.  If the block is invalid/notpresent, the
140// function returns the 0 address
141Addr
142CacheMemory::getAddressAtIdx(int idx) const
143{
144    Addr tmp(0);
145
146    int set = idx / m_cache_assoc;
147    assert(set < m_cache_num_sets);
148
149    int way = idx - set * m_cache_assoc;
150    assert (way < m_cache_assoc);
151
152    AbstractCacheEntry* entry = m_cache[set][way];
153    if (entry == NULL ||
154        entry->m_Permission == AccessPermission_Invalid ||
155        entry->m_Permission == AccessPermission_NotPresent) {
156        return tmp;
157    }
158    return entry->m_Address;
159}
160
161bool
162CacheMemory::tryCacheAccess(Addr address, RubyRequestType type,
163                            DataBlock*& data_ptr)
164{
165    assert(address == makeLineAddress(address));
166    DPRINTF(RubyCache, "address: %s\n", address);
167    int64_t cacheSet = addressToCacheSet(address);
168    int loc = findTagInSet(cacheSet, address);
169    if (loc != -1) {
170        // Do we even have a tag match?
171        AbstractCacheEntry* entry = m_cache[cacheSet][loc];
172        m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
173        data_ptr = &(entry->getDataBlk());
174
175        if (entry->m_Permission == AccessPermission_Read_Write) {
176            return true;
177        }
178        if ((entry->m_Permission == AccessPermission_Read_Only) &&
179            (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) {
180            return true;
181        }
182        // The line must not be accessible
183    }
184    data_ptr = NULL;
185    return false;
186}
187
188bool
189CacheMemory::testCacheAccess(Addr address, RubyRequestType type,
190                             DataBlock*& data_ptr)
191{
192    assert(address == makeLineAddress(address));
193    DPRINTF(RubyCache, "address: %s\n", address);
194    int64_t cacheSet = addressToCacheSet(address);
195    int loc = findTagInSet(cacheSet, address);
196
197    if (loc != -1) {
198        // Do we even have a tag match?
199        AbstractCacheEntry* entry = m_cache[cacheSet][loc];
200        m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
201        data_ptr = &(entry->getDataBlk());
202
203        return m_cache[cacheSet][loc]->m_Permission !=
204            AccessPermission_NotPresent;
205    }
206
207    data_ptr = NULL;
208    return false;
209}
210
211// tests to see if an address is present in the cache
212bool
213CacheMemory::isTagPresent(Addr address) const
214{
215    assert(address == makeLineAddress(address));
216    int64_t cacheSet = addressToCacheSet(address);
217    int loc = findTagInSet(cacheSet, address);
218
219    if (loc == -1) {
220        // We didn't find the tag
221        DPRINTF(RubyCache, "No tag match for address: %s\n", address);
222        return false;
223    }
224    DPRINTF(RubyCache, "address: %s found\n", address);
225    return true;
226}
227
228// Returns true if there is:
229//   a) a tag match on this address or there is
230//   b) an unused line in the same cache "way"
231bool
232CacheMemory::cacheAvail(Addr address) const
233{
234    assert(address == makeLineAddress(address));
235
236    int64_t cacheSet = addressToCacheSet(address);
237
238    for (int i = 0; i < m_cache_assoc; i++) {
239        AbstractCacheEntry* entry = m_cache[cacheSet][i];
240        if (entry != NULL) {
241            if (entry->m_Address == address ||
242                entry->m_Permission == AccessPermission_NotPresent) {
243                // Already in the cache or we found an empty entry
244                return true;
245            }
246        } else {
247            return true;
248        }
249    }
250    return false;
251}
252
253AbstractCacheEntry*
254CacheMemory::allocate(Addr address, AbstractCacheEntry* entry, bool touch)
255{
256    assert(address == makeLineAddress(address));
257    assert(!isTagPresent(address));
258    assert(cacheAvail(address));
259    DPRINTF(RubyCache, "address: %s\n", address);
260
261    // Find the first open slot
262    int64_t cacheSet = addressToCacheSet(address);
263    std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet];
264    for (int i = 0; i < m_cache_assoc; i++) {
265        if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) {
266            set[i] = entry;  // Init entry
267            set[i]->m_Address = address;
268            set[i]->m_Permission = AccessPermission_Invalid;
269            DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n",
270                    address);
271            set[i]->m_locked = -1;
272            m_tag_index[address] = i;
273
274            if (touch) {
275                m_replacementPolicy_ptr->touch(cacheSet, i, curTick());
276            }
277
278            return entry;
279        }
280    }
281    panic("Allocate didn't find an available entry");
282}
283
284void
285CacheMemory::deallocate(Addr address)
286{
287    assert(address == makeLineAddress(address));
288    assert(isTagPresent(address));
289    DPRINTF(RubyCache, "address: %s\n", address);
290    int64_t cacheSet = addressToCacheSet(address);
291    int loc = findTagInSet(cacheSet, address);
292    if (loc != -1) {
293        delete m_cache[cacheSet][loc];
294        m_cache[cacheSet][loc] = NULL;
295        m_tag_index.erase(address);
296    }
297}
298
299// Returns with the physical address of the conflicting cache line
300Addr
301CacheMemory::cacheProbe(Addr address) const
302{
303    assert(address == makeLineAddress(address));
304    assert(!cacheAvail(address));
305
306    int64_t cacheSet = addressToCacheSet(address);
307    return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]->
308        m_Address;
309}
310
311// looks an address up in the cache
312AbstractCacheEntry*
313CacheMemory::lookup(Addr address)
314{
315    assert(address == makeLineAddress(address));
316    int64_t cacheSet = addressToCacheSet(address);
317    int loc = findTagInSet(cacheSet, address);
318    if(loc == -1) return NULL;
319    return m_cache[cacheSet][loc];
320}
321
322// looks an address up in the cache
323const AbstractCacheEntry*
324CacheMemory::lookup(Addr address) const
325{
326    assert(address == makeLineAddress(address));
327    int64_t cacheSet = addressToCacheSet(address);
328    int loc = findTagInSet(cacheSet, address);
329    if(loc == -1) return NULL;
330    return m_cache[cacheSet][loc];
331}
332
333// Sets the most recently used bit for a cache block
334void
335CacheMemory::setMRU(Addr address)
336{
337    int64_t cacheSet = addressToCacheSet(address);
338    int loc = findTagInSet(cacheSet, address);
339
340    if(loc != -1)
341        m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
342}
343
344void
345CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
346{
347    uint64_t warmedUpBlocks = 0;
348    uint64_t totalBlocks M5_VAR_USED = (uint64_t)m_cache_num_sets *
349                                       (uint64_t)m_cache_assoc;
350
351    for (int i = 0; i < m_cache_num_sets; i++) {
352        for (int j = 0; j < m_cache_assoc; j++) {
353            if (m_cache[i][j] != NULL) {
354                AccessPermission perm = m_cache[i][j]->m_Permission;
355                RubyRequestType request_type = RubyRequestType_NULL;
356                if (perm == AccessPermission_Read_Only) {
357                    if (m_is_instruction_only_cache) {
358                        request_type = RubyRequestType_IFETCH;
359                    } else {
360                        request_type = RubyRequestType_LD;
361                    }
362                } else if (perm == AccessPermission_Read_Write) {
363                    request_type = RubyRequestType_ST;
364                }
365
366                if (request_type != RubyRequestType_NULL) {
367                    tr->addRecord(cntrl, m_cache[i][j]->m_Address,
368                                  0, request_type,
369                                  m_replacementPolicy_ptr->getLastAccess(i, j),
370                                  m_cache[i][j]->getDataBlk());
371                    warmedUpBlocks++;
372                }
373            }
374        }
375    }
376
377    DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks"
378            "recorded %.2f%% \n", name().c_str(), warmedUpBlocks,
379            totalBlocks, (float(warmedUpBlocks) / float(totalBlocks)) * 100.0);
380}
381
382void
383CacheMemory::print(ostream& out) const
384{
385    out << "Cache dump: " << name() << endl;
386    for (int i = 0; i < m_cache_num_sets; i++) {
387        for (int j = 0; j < m_cache_assoc; j++) {
388            if (m_cache[i][j] != NULL) {
389                out << "  Index: " << i
390                    << " way: " << j
391                    << " entry: " << *m_cache[i][j] << endl;
392            } else {
393                out << "  Index: " << i
394                    << " way: " << j
395                    << " entry: NULL" << endl;
396            }
397        }
398    }
399}
400
401void
402CacheMemory::printData(ostream& out) const
403{
404    out << "printData() not supported" << endl;
405}
406
407void
408CacheMemory::setLocked(Addr address, int context)
409{
410    DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
411    assert(address == makeLineAddress(address));
412    int64_t cacheSet = addressToCacheSet(address);
413    int loc = findTagInSet(cacheSet, address);
414    assert(loc != -1);
415    m_cache[cacheSet][loc]->setLocked(context);
416}
417
418void
419CacheMemory::clearLocked(Addr address)
420{
421    DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
422    assert(address == makeLineAddress(address));
423    int64_t cacheSet = addressToCacheSet(address);
424    int loc = findTagInSet(cacheSet, address);
425    assert(loc != -1);
426    m_cache[cacheSet][loc]->clearLocked();
427}
428
429bool
430CacheMemory::isLocked(Addr address, int context)
431{
432    assert(address == makeLineAddress(address));
433    int64_t cacheSet = addressToCacheSet(address);
434    int loc = findTagInSet(cacheSet, address);
435    assert(loc != -1);
436    DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
437            address, m_cache[cacheSet][loc]->m_locked, context);
438    return m_cache[cacheSet][loc]->isLocked(context);
439}
440
441void
442CacheMemory::regStats()
443{
444    m_demand_hits
445        .name(name() + ".demand_hits")
446        .desc("Number of cache demand hits")
447        ;
448
449    m_demand_misses
450        .name(name() + ".demand_misses")
451        .desc("Number of cache demand misses")
452        ;
453
454    m_demand_accesses
455        .name(name() + ".demand_accesses")
456        .desc("Number of cache demand accesses")
457        ;
458
459    m_demand_accesses = m_demand_hits + m_demand_misses;
460
461    m_sw_prefetches
462        .name(name() + ".total_sw_prefetches")
463        .desc("Number of software prefetches")
464        .flags(Stats::nozero)
465        ;
466
467    m_hw_prefetches
468        .name(name() + ".total_hw_prefetches")
469        .desc("Number of hardware prefetches")
470        .flags(Stats::nozero)
471        ;
472
473    m_prefetches
474        .name(name() + ".total_prefetches")
475        .desc("Number of prefetches")
476        .flags(Stats::nozero)
477        ;
478
479    m_prefetches = m_sw_prefetches + m_hw_prefetches;
480
481    m_accessModeType
482        .init(RubyRequestType_NUM)
483        .name(name() + ".access_mode")
484        .flags(Stats::pdf | Stats::total)
485        ;
486    for (int i = 0; i < RubyAccessMode_NUM; i++) {
487        m_accessModeType
488            .subname(i, RubyAccessMode_to_string(RubyAccessMode(i)))
489            .flags(Stats::nozero)
490            ;
491    }
492
493    numDataArrayReads
494        .name(name() + ".num_data_array_reads")
495        .desc("number of data array reads")
496        .flags(Stats::nozero)
497        ;
498
499    numDataArrayWrites
500        .name(name() + ".num_data_array_writes")
501        .desc("number of data array writes")
502        .flags(Stats::nozero)
503        ;
504
505    numTagArrayReads
506        .name(name() + ".num_tag_array_reads")
507        .desc("number of tag array reads")
508        .flags(Stats::nozero)
509        ;
510
511    numTagArrayWrites
512        .name(name() + ".num_tag_array_writes")
513        .desc("number of tag array writes")
514        .flags(Stats::nozero)
515        ;
516
517    numTagArrayStalls
518        .name(name() + ".num_tag_array_stalls")
519        .desc("number of stalls caused by tag array")
520        .flags(Stats::nozero)
521        ;
522
523    numDataArrayStalls
524        .name(name() + ".num_data_array_stalls")
525        .desc("number of stalls caused by data array")
526        .flags(Stats::nozero)
527        ;
528}
529
530// assumption: SLICC generated files will only call this function
531// once **all** resources are granted
532void
533CacheMemory::recordRequestType(CacheRequestType requestType, Addr addr)
534{
535    DPRINTF(RubyStats, "Recorded statistic: %s\n",
536            CacheRequestType_to_string(requestType));
537    switch(requestType) {
538    case CacheRequestType_DataArrayRead:
539        if (m_resource_stalls)
540            dataArray.reserve(addressToCacheSet(addr));
541        numDataArrayReads++;
542        return;
543    case CacheRequestType_DataArrayWrite:
544        if (m_resource_stalls)
545            dataArray.reserve(addressToCacheSet(addr));
546        numDataArrayWrites++;
547        return;
548    case CacheRequestType_TagArrayRead:
549        if (m_resource_stalls)
550            tagArray.reserve(addressToCacheSet(addr));
551        numTagArrayReads++;
552        return;
553    case CacheRequestType_TagArrayWrite:
554        if (m_resource_stalls)
555            tagArray.reserve(addressToCacheSet(addr));
556        numTagArrayWrites++;
557        return;
558    default:
559        warn("CacheMemory access_type not found: %s",
560             CacheRequestType_to_string(requestType));
561    }
562}
563
564bool
565CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
566{
567    if (!m_resource_stalls) {
568        return true;
569    }
570
571    if (res == CacheResourceType_TagArray) {
572        if (tagArray.tryAccess(addressToCacheSet(addr))) return true;
573        else {
574            DPRINTF(RubyResourceStalls,
575                    "Tag array stall on addr %s in set %d\n",
576                    addr, addressToCacheSet(addr));
577            numTagArrayStalls++;
578            return false;
579        }
580    } else if (res == CacheResourceType_DataArray) {
581        if (dataArray.tryAccess(addressToCacheSet(addr))) return true;
582        else {
583            DPRINTF(RubyResourceStalls,
584                    "Data array stall on addr %s in set %d\n",
585                    addr, addressToCacheSet(addr));
586            numDataArrayStalls++;
587            return false;
588        }
589    } else {
590        assert(false);
591        return true;
592    }
593}
594
595bool
596CacheMemory::isBlockInvalid(int64_t cache_set, int64_t loc)
597{
598  return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid);
599}
600
601bool
602CacheMemory::isBlockNotBusy(int64_t cache_set, int64_t loc)
603{
604  return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy);
605}
606