BankedArray.hh revision 10441:5377550e1e15
12929Sktlim@umich.edu/* 22929Sktlim@umich.edu * Copyright (c) 2012 Advanced Micro Devices, Inc. 32932Sktlim@umich.edu * All rights reserved. 42929Sktlim@umich.edu * 52929Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 62929Sktlim@umich.edu * modification, are permitted provided that the following conditions are 72929Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 82929Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 92929Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 102929Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 112929Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 122929Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 132929Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 142929Sktlim@umich.edu * this software without specific prior written permission. 152929Sktlim@umich.edu * 162929Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172929Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182929Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192929Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202929Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212929Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222929Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232929Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242929Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252929Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262929Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272929Sktlim@umich.edu * 282932Sktlim@umich.edu * Author: Brad Beckmann 292932Sktlim@umich.edu * 302932Sktlim@umich.edu */ 312929Sktlim@umich.edu 326007Ssteve.reinhardt@amd.com#ifndef __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__ 337735SAli.Saidi@ARM.com#define __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__ 342929Sktlim@umich.edu 352929Sktlim@umich.edu#include <vector> 362929Sktlim@umich.edu 372929Sktlim@umich.edu#include "mem/ruby/common/TypeDefines.hh" 382929Sktlim@umich.edu#include "sim/core.hh" 392929Sktlim@umich.edu 402929Sktlim@umich.educlass BankedArray 418947Sandreas.hansson@arm.com{ 428947Sandreas.hansson@arm.com private: 438947Sandreas.hansson@arm.com unsigned int banks; 442929Sktlim@umich.edu Cycles accessLatency; 452929Sktlim@umich.edu unsigned int bankBits; 462929Sktlim@umich.edu unsigned int startIndexBit; 472929Sktlim@umich.edu 482929Sktlim@umich.edu class AccessRecord 492929Sktlim@umich.edu { 506007Ssteve.reinhardt@amd.com public: 516007Ssteve.reinhardt@amd.com AccessRecord() : idx(0), startAccess(0), endAccess(0) {} 526007Ssteve.reinhardt@amd.com int64 idx; 536007Ssteve.reinhardt@amd.com Tick startAccess; 546007Ssteve.reinhardt@amd.com Tick endAccess; 556007Ssteve.reinhardt@amd.com }; 566007Ssteve.reinhardt@amd.com 576007Ssteve.reinhardt@amd.com // If the tick event is scheduled then the bank is busy 586007Ssteve.reinhardt@amd.com // otherwise, schedule the event and wait for it to complete 596007Ssteve.reinhardt@amd.com std::vector<AccessRecord> busyBanks; 606007Ssteve.reinhardt@amd.com 616007Ssteve.reinhardt@amd.com unsigned int mapIndexToBank(int64 idx); 626007Ssteve.reinhardt@amd.com 636007Ssteve.reinhardt@amd.com public: 646007Ssteve.reinhardt@amd.com BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit); 656007Ssteve.reinhardt@amd.com 669435SAndreas.Sandberg@ARM.com // Note: We try the access based on the cache index, not the address 679435SAndreas.Sandberg@ARM.com // This is so we don't get aliasing on blocks being replaced 689435SAndreas.Sandberg@ARM.com bool tryAccess(int64 idx); 696007Ssteve.reinhardt@amd.com 706007Ssteve.reinhardt@amd.com}; 716007Ssteve.reinhardt@amd.com 726007Ssteve.reinhardt@amd.com#endif 736007Ssteve.reinhardt@amd.com