BankedArray.hh revision 10301:44839e8febbd
1955SN/A/* 2955SN/A * Copyright (c) 2012 Advanced Micro Devices, Inc. 31762SN/A * All rights reserved. 4955SN/A * 5955SN/A * Redistribution and use in source and binary forms, with or without 6955SN/A * modification, are permitted provided that the following conditions are 7955SN/A * met: redistributions of source code must retain the above copyright 8955SN/A * notice, this list of conditions and the following disclaimer; 9955SN/A * redistributions in binary form must reproduce the above copyright 10955SN/A * notice, this list of conditions and the following disclaimer in the 11955SN/A * documentation and/or other materials provided with the distribution; 12955SN/A * neither the name of the copyright holders nor the names of its 13955SN/A * contributors may be used to endorse or promote products derived from 14955SN/A * this software without specific prior written permission. 15955SN/A * 16955SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17955SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23955SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24955SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25955SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26955SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27955SN/A * 282665Ssaidi@eecs.umich.edu * Author: Brad Beckmann 292665Ssaidi@eecs.umich.edu * 30955SN/A */ 31955SN/A 32955SN/A#ifndef __MEM_RUBY_SYSTEM_BANKEDARRAY_HH__ 33955SN/A#define __MEM_RUBY_SYSTEM_BANKEDARRAY_HH__ 34955SN/A 352632Sstever@eecs.umich.edu#include <vector> 362632Sstever@eecs.umich.edu 372632Sstever@eecs.umich.edu#include "mem/ruby/common/TypeDefines.hh" 382632Sstever@eecs.umich.edu#include "sim/core.hh" 39955SN/A 402632Sstever@eecs.umich.educlass BankedArray 412632Sstever@eecs.umich.edu{ 422761Sstever@eecs.umich.edu private: 432632Sstever@eecs.umich.edu unsigned int banks; 442632Sstever@eecs.umich.edu Cycles accessLatency; 452632Sstever@eecs.umich.edu unsigned int bankBits; 462761Sstever@eecs.umich.edu unsigned int startIndexBit; 472761Sstever@eecs.umich.edu 482761Sstever@eecs.umich.edu class AccessRecord 492632Sstever@eecs.umich.edu { 502632Sstever@eecs.umich.edu public: 512761Sstever@eecs.umich.edu AccessRecord() : idx(0), startAccess(0), endAccess(0) {} 522761Sstever@eecs.umich.edu Index idx; 532761Sstever@eecs.umich.edu Tick startAccess; 542761Sstever@eecs.umich.edu Tick endAccess; 552761Sstever@eecs.umich.edu }; 562632Sstever@eecs.umich.edu 572632Sstever@eecs.umich.edu // If the tick event is scheduled then the bank is busy 582632Sstever@eecs.umich.edu // otherwise, schedule the event and wait for it to complete 592632Sstever@eecs.umich.edu std::vector<AccessRecord> busyBanks; 602632Sstever@eecs.umich.edu 612632Sstever@eecs.umich.edu unsigned int mapIndexToBank(Index idx); 622632Sstever@eecs.umich.edu 63955SN/A public: 64955SN/A BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit); 65955SN/A 66955SN/A // Note: We try the access based on the cache index, not the address 67955SN/A // This is so we don't get aliasing on blocks being replaced 684202Sbinkertn@umich.edu bool tryAccess(Index idx); 694678Snate@binkert.org 70955SN/A}; 715273Sstever@gmail.com 725273Sstever@gmail.com#endif 732656Sstever@eecs.umich.edu