RubySlicc_ComponentMapping.hh revision 7805:f249937228b5 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
30#define __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
31
32#include "mem/protocol/GenericMachineType.hh"
33#include "mem/protocol/MachineType.hh"
34#include "mem/ruby/common/Address.hh"
35#include "mem/ruby/common/Global.hh"
36#include "mem/ruby/common/NetDest.hh"
37#include "mem/ruby/common/Set.hh"
38#include "mem/ruby/system/DirectoryMemory.hh"
39#include "mem/ruby/system/MachineID.hh"
40#include "mem/ruby/system/NodeID.hh"
41
42#ifdef MACHINETYPE_L1Cache
43#define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache
44#else
45#define MACHINETYPE_L1CACHE_ENUM MachineType_NUM
46#endif
47
48#ifdef MACHINETYPE_L2Cache
49#define MACHINETYPE_L2CACHE_ENUM MachineType_L2Cache
50#else
51#define MACHINETYPE_L2CACHE_ENUM MachineType_NUM
52#endif
53
54#ifdef MACHINETYPE_L3Cache
55#define MACHINETYPE_L3CACHE_ENUM MachineType_L3Cache
56#else
57#define MACHINETYPE_L3CACHE_ENUM MachineType_NUM
58#endif
59
60#ifdef MACHINETYPE_DMA
61#define MACHINETYPE_DMA_ENUM MachineType_DMA
62#else
63#define MACHINETYPE_DMA_ENUM MachineType_NUM
64#endif
65
66// used to determine the home directory
67// returns a value between 0 and total_directories_within_the_system
68inline NodeID
69map_Address_to_DirectoryNode(const Address& addr)
70{
71    return DirectoryMemory::mapAddressToDirectoryVersion(addr);
72}
73
74// used to determine the home directory
75// returns a value between 0 and total_directories_within_the_system
76inline MachineID
77map_Address_to_Directory(const Address &addr)
78{
79    MachineID mach =
80        {MachineType_Directory, map_Address_to_DirectoryNode(addr)};
81    return mach;
82}
83
84inline MachineID
85map_Address_to_DMA(const Address & addr)
86{
87    MachineID dma = {MACHINETYPE_DMA_ENUM, 0};
88    return dma;
89}
90
91inline NetDest
92broadcast(MachineType type)
93{
94    NetDest dest;
95    for (int i = 0; i < MachineType_base_count(type); i++) {
96        MachineID mach = {type, i};
97        dest.add(mach);
98    }
99    return dest;
100}
101
102inline MachineID
103mapAddressToRange(const Address & addr, MachineType type, int low_bit,
104                  int num_bits)
105{
106    MachineID mach = {type, 0};
107    if (num_bits == 0)
108        return mach;
109    mach.num = addr.bitSelect(low_bit, low_bit + num_bits - 1);
110    return mach;
111}
112
113inline NodeID
114machineIDToNodeID(MachineID machID)
115{
116    return machID.num;
117}
118
119inline MachineType
120machineIDToMachineType(MachineID machID)
121{
122    return machID.type;
123}
124
125inline NodeID
126L1CacheMachIDToProcessorNum(MachineID machID)
127{
128    assert(machID.type == MachineType_L1Cache);
129    return machID.num;
130}
131
132inline MachineID
133getL1MachineID(NodeID L1RubyNode)
134{
135    MachineID mach = {MACHINETYPE_L1CACHE_ENUM, L1RubyNode};
136    return mach;
137}
138
139inline GenericMachineType
140ConvertMachToGenericMach(MachineType machType)
141{
142    if (machType == MACHINETYPE_L1CACHE_ENUM)
143        return GenericMachineType_L1Cache;
144
145    if (machType == MACHINETYPE_L2CACHE_ENUM)
146        return GenericMachineType_L2Cache;
147
148    if (machType == MACHINETYPE_L3CACHE_ENUM)
149        return GenericMachineType_L3Cache;
150
151    if (machType == MachineType_Directory)
152        return GenericMachineType_Directory;
153
154    panic("cannot convert to a GenericMachineType");
155}
156
157inline int
158machineCount(MachineType machType)
159{
160    return MachineType_base_count(machType);
161}
162
163#endif  // __MEM_RUBY_SLICC_INTERFACE_COMPONENTMAPPINGS_HH__
164