Controller.py revision 12065
112065Snikos.nikoleris@arm.com# Copyright (c) 2017 ARM Limited 212065Snikos.nikoleris@arm.com# All rights reserved. 312065Snikos.nikoleris@arm.com# 412065Snikos.nikoleris@arm.com# The license below extends only to copyright in the software and shall 512065Snikos.nikoleris@arm.com# not be construed as granting a license to any other intellectual 612065Snikos.nikoleris@arm.com# property including but not limited to intellectual property relating 712065Snikos.nikoleris@arm.com# to a hardware implementation of the functionality of the software 812065Snikos.nikoleris@arm.com# licensed hereunder. You may use the software subject to the license 912065Snikos.nikoleris@arm.com# terms below provided that you ensure that this notice is replicated 1012065Snikos.nikoleris@arm.com# unmodified and in its entirety in all distributions of the software, 1112065Snikos.nikoleris@arm.com# modified or unmodified, in source code or in binary form. 1212065Snikos.nikoleris@arm.com# 137019SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 147019SBrad.Beckmann@amd.com# All rights reserved. 157019SBrad.Beckmann@amd.com# 167019SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 177019SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 187019SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 197019SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 207019SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 217019SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 227019SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 237019SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 247019SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 257019SBrad.Beckmann@amd.com# this software without specific prior written permission. 267019SBrad.Beckmann@amd.com# 277019SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 287019SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 297019SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 307019SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 317019SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 327019SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 337019SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 347019SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 357019SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 367019SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 377019SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 387019SBrad.Beckmann@amd.com# 397019SBrad.Beckmann@amd.com# Authors: Steve Reinhardt 407019SBrad.Beckmann@amd.com# Brad Beckmann 417019SBrad.Beckmann@amd.com 426876Ssteve.reinhardt@amd.comfrom m5.params import * 4310524Snilay@cs.wisc.edufrom m5.proxy import * 4410524Snilay@cs.wisc.edufrom MemObject import MemObject 456876Ssteve.reinhardt@amd.com 4610524Snilay@cs.wisc.educlass RubyController(MemObject): 476876Ssteve.reinhardt@amd.com type = 'RubyController' 486876Ssteve.reinhardt@amd.com cxx_class = 'AbstractController' 499338SAndreas.Sandberg@arm.com cxx_header = "mem/ruby/slicc_interface/AbstractController.hh" 506876Ssteve.reinhardt@amd.com abstract = True 516876Ssteve.reinhardt@amd.com version = Param.Int("") 5212065Snikos.nikoleris@arm.com addr_ranges = VectorParam.AddrRange([AllMemory], "Address range this " 5312065Snikos.nikoleris@arm.com "controller responds to") 5410005Snilay@cs.wisc.edu cluster_id = Param.UInt32(0, "Id of this controller's cluster") 5510005Snilay@cs.wisc.edu 566876Ssteve.reinhardt@amd.com transitions_per_cycle = \ 576876Ssteve.reinhardt@amd.com Param.Int(32, "no. of SLICC state machine transitions per cycle") 5810096Snilay@cs.wisc.edu buffer_size = Param.UInt32(0, "max buffer size 0 means infinite") 5910096Snilay@cs.wisc.edu 609499Snilay@cs.wisc.edu recycle_latency = Param.Cycles(10, "") 616876Ssteve.reinhardt@amd.com number_of_TBEs = Param.Int(256, "") 629595Snilay@cs.wisc.edu ruby_system = Param.RubySystem("") 639595Snilay@cs.wisc.edu 6410524Snilay@cs.wisc.edu memory = MasterPort("Port for attaching a memory controller") 6510524Snilay@cs.wisc.edu system = Param.System(Parent.any, "system object parameter") 66