AbstractController.cc revision 10311:ad9c042dce54
1/* 2 * Copyright (c) 2011 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "mem/ruby/slicc_interface/AbstractController.hh" 30#include "mem/ruby/system/Sequencer.hh" 31#include "mem/ruby/system/System.hh" 32 33AbstractController::AbstractController(const Params *p) 34 : ClockedObject(p), Consumer(this) 35{ 36 m_version = p->version; 37 m_clusterID = p->cluster_id; 38 39 m_transitions_per_cycle = p->transitions_per_cycle; 40 m_buffer_size = p->buffer_size; 41 m_recycle_latency = p->recycle_latency; 42 m_number_of_TBEs = p->number_of_TBEs; 43 m_is_blocking = false; 44 45 if (m_version == 0) { 46 // Combine the statistics from all controllers 47 // of this particular type. 48 Stats::registerDumpCallback(new StatsCallback(this)); 49 } 50} 51 52void 53AbstractController::init() 54{ 55 params()->ruby_system->registerAbstractController(this); 56 m_delayHistogram.init(10); 57 uint32_t size = Network::getNumberOfVirtualNetworks(); 58 for (uint32_t i = 0; i < size; i++) { 59 m_delayVCHistogram.push_back(new Stats::Histogram()); 60 m_delayVCHistogram[i]->init(10); 61 } 62} 63 64void 65AbstractController::resetStats() 66{ 67 m_delayHistogram.reset(); 68 uint32_t size = Network::getNumberOfVirtualNetworks(); 69 for (uint32_t i = 0; i < size; i++) { 70 m_delayVCHistogram[i]->reset(); 71 } 72} 73 74void 75AbstractController::regStats() 76{ 77 m_fully_busy_cycles 78 .name(name() + ".fully_busy_cycles") 79 .desc("cycles for which number of transistions == max transitions") 80 .flags(Stats::nozero); 81} 82 83void 84AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay) 85{ 86 assert(virtualNetwork < m_delayVCHistogram.size()); 87 m_delayHistogram.sample(delay); 88 m_delayVCHistogram[virtualNetwork]->sample(delay); 89} 90 91void 92AbstractController::stallBuffer(MessageBuffer* buf, Address addr) 93{ 94 if (m_waiting_buffers.count(addr) == 0) { 95 MsgVecType* msgVec = new MsgVecType; 96 msgVec->resize(m_in_ports, NULL); 97 m_waiting_buffers[addr] = msgVec; 98 } 99 (*(m_waiting_buffers[addr]))[m_cur_in_port] = buf; 100} 101 102void 103AbstractController::wakeUpBuffers(Address addr) 104{ 105 if (m_waiting_buffers.count(addr) > 0) { 106 // 107 // Wake up all possible lower rank (i.e. lower priority) buffers that could 108 // be waiting on this message. 109 // 110 for (int in_port_rank = m_cur_in_port - 1; 111 in_port_rank >= 0; 112 in_port_rank--) { 113 if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) { 114 (*(m_waiting_buffers[addr]))[in_port_rank]->reanalyzeMessages(addr); 115 } 116 } 117 delete m_waiting_buffers[addr]; 118 m_waiting_buffers.erase(addr); 119 } 120} 121 122void 123AbstractController::wakeUpAllBuffers(Address addr) 124{ 125 if (m_waiting_buffers.count(addr) > 0) { 126 // 127 // Wake up all possible lower rank (i.e. lower priority) buffers that could 128 // be waiting on this message. 129 // 130 for (int in_port_rank = m_in_ports - 1; 131 in_port_rank >= 0; 132 in_port_rank--) { 133 if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) { 134 (*(m_waiting_buffers[addr]))[in_port_rank]->reanalyzeMessages(addr); 135 } 136 } 137 delete m_waiting_buffers[addr]; 138 m_waiting_buffers.erase(addr); 139 } 140} 141 142void 143AbstractController::wakeUpAllBuffers() 144{ 145 // 146 // Wake up all possible buffers that could be waiting on any message. 147 // 148 149 std::vector<MsgVecType*> wokeUpMsgVecs; 150 151 if(m_waiting_buffers.size() > 0) { 152 for (WaitingBufType::iterator buf_iter = m_waiting_buffers.begin(); 153 buf_iter != m_waiting_buffers.end(); 154 ++buf_iter) { 155 for (MsgVecType::iterator vec_iter = buf_iter->second->begin(); 156 vec_iter != buf_iter->second->end(); 157 ++vec_iter) { 158 if (*vec_iter != NULL) { 159 (*vec_iter)->reanalyzeAllMessages(); 160 } 161 } 162 wokeUpMsgVecs.push_back(buf_iter->second); 163 } 164 165 for (std::vector<MsgVecType*>::iterator wb_iter = wokeUpMsgVecs.begin(); 166 wb_iter != wokeUpMsgVecs.end(); 167 ++wb_iter) { 168 delete (*wb_iter); 169 } 170 171 m_waiting_buffers.clear(); 172 } 173} 174 175void 176AbstractController::blockOnQueue(Address addr, MessageBuffer* port) 177{ 178 m_is_blocking = true; 179 m_block_map[addr] = port; 180} 181 182void 183AbstractController::unblock(Address addr) 184{ 185 m_block_map.erase(addr); 186 if (m_block_map.size() == 0) { 187 m_is_blocking = false; 188 } 189} 190