AbstractCacheEntry.hh revision 11308:7d8836fd043d
14403Srdreslin@umich.edu/* 21693Sstever@eecs.umich.edu * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 31693Sstever@eecs.umich.edu * All rights reserved. 41693Sstever@eecs.umich.edu * 51693Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 61693Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 71693Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 81693Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 91693Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 101693Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 111693Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 121693Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 131693Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 141693Sstever@eecs.umich.edu * this software without specific prior written permission. 151693Sstever@eecs.umich.edu * 161693Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171693Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181693Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191693Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201693Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211693Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221693Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231693Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241693Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251693Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261693Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271693Sstever@eecs.umich.edu */ 281693Sstever@eecs.umich.edu 293358Srdreslin@umich.edu/* 303358Srdreslin@umich.edu * Common base class for a machine node. 311516SN/A */ 323358Srdreslin@umich.edu 333358Srdreslin@umich.edu#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__ 343358Srdreslin@umich.edu#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__ 353358Srdreslin@umich.edu 361516SN/A#include <iostream> 373358Srdreslin@umich.edu 383358Srdreslin@umich.edu#include "base/misc.hh" 393358Srdreslin@umich.edu#include "mem/protocol/AccessPermission.hh" 403358Srdreslin@umich.edu#include "mem/ruby/common/Address.hh" 413358Srdreslin@umich.edu#include "mem/ruby/slicc_interface/AbstractEntry.hh" 423358Srdreslin@umich.edu 433358Srdreslin@umich.educlass DataBlock; 443358Srdreslin@umich.edu 453358Srdreslin@umich.educlass AbstractCacheEntry : public AbstractEntry 463358Srdreslin@umich.edu{ 473358Srdreslin@umich.edu public: 483358Srdreslin@umich.edu AbstractCacheEntry(); 493360Srdreslin@umich.edu virtual ~AbstractCacheEntry() = 0; 503358Srdreslin@umich.edu 513358Srdreslin@umich.edu // Get/Set permission of the entry 523358Srdreslin@umich.edu void changePermission(AccessPermission new_perm); 533358Srdreslin@umich.edu 543360Srdreslin@umich.edu // The methods below are those called by ruby runtime, add when it 553360Srdreslin@umich.edu // is absolutely necessary and should all be virtual function. 563360Srdreslin@umich.edu virtual DataBlock& getDataBlk() 573360Srdreslin@umich.edu { panic("getDataBlk() not implemented!"); } 583360Srdreslin@umich.edu 593360Srdreslin@umich.edu int validBlocks; 603360Srdreslin@umich.edu virtual int& getNumValidBlocks() 613360Srdreslin@umich.edu { 623358Srdreslin@umich.edu return validBlocks; 634403Srdreslin@umich.edu } 643360Srdreslin@umich.edu 653358Srdreslin@umich.edu // Functions for locking and unlocking the cache entry. These are required 663358Srdreslin@umich.edu // for supporting atomic memory accesses. 673358Srdreslin@umich.edu void setLocked(int context); 683358Srdreslin@umich.edu void clearLocked(); 693358Srdreslin@umich.edu bool isLocked(int context) const; 703358Srdreslin@umich.edu 713358Srdreslin@umich.edu void setSetIndex(uint32_t s) { m_set_index = s; } 723358Srdreslin@umich.edu uint32_t getSetIndex() const { return m_set_index; } 733358Srdreslin@umich.edu 743360Srdreslin@umich.edu void setWayIndex(uint32_t s) { m_way_index = s; } 753360Srdreslin@umich.edu uint32_t getWayIndex() const { return m_way_index; } 763360Srdreslin@umich.edu 773360Srdreslin@umich.edu // Address of this block, required by CacheMemory 783358Srdreslin@umich.edu Addr m_Address; 793358Srdreslin@umich.edu // Holds info whether the address is locked. 803358Srdreslin@umich.edu // Required for implementing LL/SC operations. 813358Srdreslin@umich.edu int m_locked; 824403Srdreslin@umich.edu 834403Srdreslin@umich.edu private: 844403Srdreslin@umich.edu // Set and way coordinates of the entry within the cache memory object. 854403Srdreslin@umich.edu uint32_t m_set_index; 863358Srdreslin@umich.edu uint32_t m_way_index; 873358Srdreslin@umich.edu}; 884403Srdreslin@umich.edu 894403Srdreslin@umich.eduinline std::ostream& 904403Srdreslin@umich.eduoperator<<(std::ostream& out, const AbstractCacheEntry& obj) 913358Srdreslin@umich.edu{ 923358Srdreslin@umich.edu obj.print(out); 934403Srdreslin@umich.edu out << std::flush; 944403Srdreslin@umich.edu return out; 954403Srdreslin@umich.edu} 963358Srdreslin@umich.edu 973358Srdreslin@umich.edu#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__ 984403Srdreslin@umich.edu