RubySlicc_MemControl.sm revision 14184
12023SN/A 22023SN/A/* 32023SN/A * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood 42023SN/A * All rights reserved. 52023SN/A * 62023SN/A * Redistribution and use in source and binary forms, with or without 72023SN/A * modification, are permitted provided that the following conditions are 82023SN/A * met: redistributions of source code must retain the above copyright 92023SN/A * notice, this list of conditions and the following disclaimer; 102023SN/A * redistributions in binary form must reproduce the above copyright 112023SN/A * notice, this list of conditions and the following disclaimer in the 122023SN/A * documentation and/or other materials provided with the distribution; 132023SN/A * neither the name of the copyright holders nor the names of its 142023SN/A * contributors may be used to endorse or promote products derived from 152023SN/A * this software without specific prior written permission. 162023SN/A * 172023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192023SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202023SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212023SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262023SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu */ 292665Ssaidi@eecs.umich.edu 302023SN/A/* 312023SN/A * $Id$ 322023SN/A * 332023SN/A */ 342023SN/A 352225SN/A// MemoryRequestType used in MemoryMsg 362225SN/A 372225SN/Aenumeration(MemoryRequestType, desc="...") { 382225SN/A 392225SN/A // Southbound request: from directory to memory cache 402023SN/A // or directory to memory or memory cache to memory 412023SN/A MEMORY_READ, desc="Read request to memory"; 422225SN/A MEMORY_WB, desc="Write back data to memory"; 432023SN/A 442225SN/A // response from memory to directory 452225SN/A // (These are currently unused!) 462023SN/A MEMORY_DATA, desc="Data read from memory"; 472458SN/A MEMORY_ACK, desc="Write to memory acknowledgement"; 482023SN/A} 492225SN/A 502225SN/A 512225SN/A// Message to and from Memory Control 522225SN/A 532225SN/Astructure(MemoryMsg, desc="...", interface="Message") { 542225SN/A Addr addr, desc="Physical address for this request"; 552225SN/A MemoryRequestType Type, desc="Type of memory request (MEMORY_READ or MEMORY_WB)"; 562225SN/A MachineID Sender, desc="What component sent the data"; 572225SN/A MachineID OriginalRequestorMachId, desc="What component originally requested"; 582225SN/A DataBlock DataBlk, desc="Data to writeback"; 592023SN/A MessageSizeType MessageSize, desc="size category of the message"; 602225SN/A // Not all fields used by all protocols: 612225SN/A PrefetchBit Prefetch, desc="Is this a prefetch request"; 622225SN/A bool ReadX, desc="Exclusive"; 632225SN/A int Acks, desc="How many acks to expect"; 642225SN/A 652225SN/A bool functionalRead(Packet *pkt) { 662023SN/A return testAndRead(addr, DataBlk, pkt); 672225SN/A } 682023SN/A 692225SN/A bool functionalWrite(Packet *pkt) { 702225SN/A return testAndWrite(addr, DataBlk, pkt); 712225SN/A } 722225SN/A} 732225SN/A