MOESI_AMD_Base-Region-dir.sm revision 14184
19243SN/A/* 211675Swendy.elsasser@arm.com * Copyright (c) 2010-2015 Advanced Micro Devices, Inc. 39243SN/A * All rights reserved. 49243SN/A * 59243SN/A * For use for simulation and test purposes only 69243SN/A * 79243SN/A * Redistribution and use in source and binary forms, with or without 89243SN/A * modification, are permitted provided that the following conditions are met: 99243SN/A * 109243SN/A * 1. Redistributions of source code must retain the above copyright notice, 119243SN/A * this list of conditions and the following disclaimer. 129243SN/A * 139243SN/A * 2. Redistributions in binary form must reproduce the above copyright notice, 149831SN/A * this list of conditions and the following disclaimer in the documentation 159831SN/A * and/or other materials provided with the distribution. 169831SN/A * 179243SN/A * 3. Neither the name of the copyright holder nor the names of its 189243SN/A * contributors may be used to endorse or promote products derived from this 199243SN/A * software without specific prior written permission. 209243SN/A * 219243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 229243SN/A * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 239243SN/A * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 249243SN/A * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 259243SN/A * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 269243SN/A * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 279243SN/A * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 289243SN/A * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 299243SN/A * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 309243SN/A * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 319243SN/A * POSSIBILITY OF SUCH DAMAGE. 329243SN/A * 339243SN/A * Authors: Lisa Hsu 349243SN/A */ 359243SN/A 369243SN/Amachine(MachineType:Directory, "AMD_Base-like protocol") 379243SN/A: DirectoryMemory * directory; 389243SN/A CacheMemory * L3CacheMemory; 399243SN/A Cycles response_latency := 5; 409243SN/A Cycles response_latency_regionDir := 1; 419243SN/A Cycles l3_hit_latency := 30; 429967SN/A bool useL3OnWT := "False"; 4310618SOmar.Naji@arm.com Cycles to_memory_controller_latency := 1; 4411555Sjungma@eit.uni-kl.de 4511678Swendy.elsasser@arm.com // From the Cores 4612266Sradhika.jagtap@arm.com MessageBuffer * requestFromCores, network="From", virtual_network="0", vnet_type="request"; 479243SN/A MessageBuffer * responseFromCores, network="From", virtual_network="2", vnet_type="response"; 489243SN/A MessageBuffer * unblockFromCores, network="From", virtual_network="4", vnet_type="unblock"; 499243SN/A 509243SN/A // To the Cores 5110146Sandreas.hansson@arm.com MessageBuffer * probeToCore, network="To", virtual_network="0", vnet_type="request"; 529243SN/A MessageBuffer * responseToCore, network="To", virtual_network="2", vnet_type="response"; 539243SN/A 5410146Sandreas.hansson@arm.com // From region buffer 5510146Sandreas.hansson@arm.com MessageBuffer * reqFromRegBuf, network="From", virtual_network="7", vnet_type="request"; 569243SN/A 579488SN/A // To Region directory 5810618SOmar.Naji@arm.com MessageBuffer * reqToRegDir, network="To", virtual_network="5", vnet_type="request"; 5910889Sandreas.hansson@arm.com MessageBuffer * reqFromRegDir, network="From", virtual_network="5", vnet_type="request"; 609488SN/A MessageBuffer * unblockToRegDir, network="To", virtual_network="4", vnet_type="unblock"; 6111677Swendy.elsasser@arm.com 629243SN/A MessageBuffer * triggerQueue; 639243SN/A MessageBuffer * L3triggerQueue; 649243SN/A MessageBuffer * responseFromMemory; 659243SN/A{ 669243SN/A // STATES 679243SN/A state_declaration(State, desc="Directory states", default="Directory_State_U") { 6810146Sandreas.hansson@arm.com U, AccessPermission:Backing_Store, desc="unblocked"; 699243SN/A BR, AccessPermission:Backing_Store, desc="got CPU read request, blocked while sent to L3"; 7010432SOmar.Naji@arm.com BW, AccessPermission:Backing_Store, desc="got CPU write request, blocked while sent to L3"; 719243SN/A BL, AccessPermission:Busy, desc="got L3 WB request"; 729243SN/A // BL is Busy because it's possible for the data only to be in the network 7310287Sandreas.hansson@arm.com // in the WB, L3 has sent it and gone on with its business in possibly I 7410287Sandreas.hansson@arm.com // state. 7510287Sandreas.hansson@arm.com BI, AccessPermission:Backing_Store, desc="Blocked waiting for inv ack from core"; 7610287Sandreas.hansson@arm.com BS_M, AccessPermission:Backing_Store, desc="blocked waiting for memory"; 7710287Sandreas.hansson@arm.com BM_M, AccessPermission:Backing_Store, desc="blocked waiting for memory"; 789243SN/A B_M, AccessPermission:Backing_Store, desc="blocked waiting for memory"; 7910287Sandreas.hansson@arm.com BP, AccessPermission:Backing_Store, desc="blocked waiting for probes, no need for memory"; 8010287Sandreas.hansson@arm.com BS_PM, AccessPermission:Backing_Store, desc="blocked waiting for probes and Memory"; 8110287Sandreas.hansson@arm.com BM_PM, AccessPermission:Backing_Store, desc="blocked waiting for probes and Memory"; 8210287Sandreas.hansson@arm.com B_PM, AccessPermission:Backing_Store, desc="blocked waiting for probes and Memory"; 8310287Sandreas.hansson@arm.com BS_Pm, AccessPermission:Backing_Store, desc="blocked waiting for probes, already got memory"; 8410287Sandreas.hansson@arm.com BM_Pm, AccessPermission:Backing_Store, desc="blocked waiting for probes, already got memory"; 8510287Sandreas.hansson@arm.com B_Pm, AccessPermission:Backing_Store, desc="blocked waiting for probes, already got memory"; 8610287Sandreas.hansson@arm.com B, AccessPermission:Backing_Store, desc="sent response, Blocked til ack"; 8710287Sandreas.hansson@arm.com 8810287Sandreas.hansson@arm.com // These are needed for when a private requests was issued before an inv was received 8910287Sandreas.hansson@arm.com // for writebacks 9010287Sandreas.hansson@arm.com BS_Pm_BL, AccessPermission:Backing_Store, desc="blocked waiting for probes, already got memory"; 9110287Sandreas.hansson@arm.com BM_Pm_BL, AccessPermission:Backing_Store, desc="blocked waiting for probes, already got memory"; 9211678Swendy.elsasser@arm.com B_Pm_BL, AccessPermission:Backing_Store, desc="blocked waiting for probes, already got memory"; 9311678Swendy.elsasser@arm.com BP_BL, AccessPermission:Backing_Store, desc="blocked waiting for probes, no need for memory"; 9411678Swendy.elsasser@arm.com // for reads 9511678Swendy.elsasser@arm.com BS_Pm_B, AccessPermission:Backing_Store, desc="blocked waiting for probes, already got memory"; 969243SN/A BM_Pm_B, AccessPermission:Backing_Store, desc="blocked waiting for probes, already got memory"; 9710146Sandreas.hansson@arm.com B_Pm_B, AccessPermission:Backing_Store, desc="blocked waiting for probes, already got memory"; 989243SN/A BP_B, AccessPermission:Backing_Store, desc="blocked waiting for probes, no need for memory"; 999243SN/A } 1009243SN/A 1019243SN/A // Events 1029243SN/A enumeration(Event, desc="Directory events") { 1039243SN/A // CPU requests 1049243SN/A RdBlkS, desc="..."; 1059243SN/A RdBlkM, desc="..."; 1069243SN/A RdBlk, desc="..."; 10710713Sandreas.hansson@arm.com WriteThrough, desc="WriteThrough Message"; 10810146Sandreas.hansson@arm.com Atomic, desc="Atomic Message"; 1099243SN/A 1109243SN/A RdBlkSP, desc="..."; 1119243SN/A RdBlkMP, desc="..."; 11210146Sandreas.hansson@arm.com RdBlkP, desc="..."; 1139243SN/A VicDirtyP, desc="..."; 1149243SN/A VicCleanP, desc="..."; 1159243SN/A WriteThroughP, desc="WriteThrough Message"; 1169243SN/A AtomicP, desc="Atomic Message"; 1179243SN/A 1189243SN/A // writebacks 1199243SN/A VicDirty, desc="..."; 1209243SN/A VicClean, desc="..."; 1219243SN/A CPUData, desc="WB data from CPU"; 1229243SN/A StaleWB, desc="WB response for a no longer valid request"; 1239243SN/A 1249243SN/A // probe responses 1259243SN/A CPUPrbResp, desc="Probe Response Msg"; 1269243SN/A LastCPUPrbResp, desc="Last Probe Response Msg"; 1279243SN/A 1289243SN/A ProbeAcksComplete, desc="Probe Acks Complete"; 1299243SN/A 1309243SN/A L3Hit, desc="Hit in L3 return data to core"; 1319243SN/A 1329243SN/A // Memory Controller 13310619Sandreas.hansson@arm.com MemData, desc="Fetched data from memory arrives"; 13410619Sandreas.hansson@arm.com WBAck, desc="Writeback Ack from memory arrives"; 13510619Sandreas.hansson@arm.com 13610619Sandreas.hansson@arm.com CoreUnblock, desc="Core received data, unblock"; 13710619Sandreas.hansson@arm.com UnblockWriteThrough, desc="unblock, self triggered"; 1389243SN/A 1399243SN/A StaleVicDirty, desc="Core invalidated before VicDirty processed"; 1409243SN/A StaleVicDirtyP, desc="Core invalidated before VicDirty processed"; 1419243SN/A 1429243SN/A // For region protocol 1439243SN/A CPUReq, desc="Generic CPU request"; 14410206Sandreas.hansson@arm.com Inv, desc="Region dir needs a block invalidated"; 14510206Sandreas.hansson@arm.com Downgrade, desc="Region dir needs a block downgraded"; 1469243SN/A 14710206Sandreas.hansson@arm.com // For private accesses (bypassed reg-dir) 14810206Sandreas.hansson@arm.com CPUReadP, desc="Initial req from core, sent to L3"; 14910206Sandreas.hansson@arm.com CPUWriteP, desc="Initial req from core, sent to L3"; 15010206Sandreas.hansson@arm.com } 15110206Sandreas.hansson@arm.com 15210206Sandreas.hansson@arm.com enumeration(RequestType, desc="To communicate stats from transitions to recordStats") { 1539243SN/A L3DataArrayRead, desc="Read the data array"; 15411678Swendy.elsasser@arm.com L3DataArrayWrite, desc="Write the data array"; 15511678Swendy.elsasser@arm.com L3TagArrayRead, desc="Read the data array"; 15611678Swendy.elsasser@arm.com L3TagArrayWrite, desc="Write the data array"; 1579243SN/A } 15811675Swendy.elsasser@arm.com 15911675Swendy.elsasser@arm.com // TYPES 16011675Swendy.elsasser@arm.com 16111675Swendy.elsasser@arm.com // DirectoryEntry 16211675Swendy.elsasser@arm.com structure(Entry, desc="...", interface="AbstractEntry") { 16311675Swendy.elsasser@arm.com State DirectoryState, desc="Directory state"; 16411675Swendy.elsasser@arm.com DataBlock DataBlk, desc="data for the block"; 16511675Swendy.elsasser@arm.com NetDest VicDirtyIgnore, desc="VicDirty coming from whom to ignore"; 16611675Swendy.elsasser@arm.com } 16711675Swendy.elsasser@arm.com 16811675Swendy.elsasser@arm.com structure(CacheEntry, desc="...", interface="AbstractCacheEntry") { 16911675Swendy.elsasser@arm.com DataBlock DataBlk, desc="data for the block"; 17011675Swendy.elsasser@arm.com MachineID LastSender, desc="Mach which this block came from"; 17111675Swendy.elsasser@arm.com } 17211675Swendy.elsasser@arm.com 17310210Sandreas.hansson@arm.com structure(TBE, desc="...") { 17410210Sandreas.hansson@arm.com State TBEState, desc="Transient state"; 17510211Sandreas.hansson@arm.com DataBlock DataBlk, desc="data for the block"; 17610211Sandreas.hansson@arm.com DataBlock DataBlkAux, desc="Auxiliary data for the block"; 17710210Sandreas.hansson@arm.com bool Dirty, desc="Is the data dirty?"; 17810210Sandreas.hansson@arm.com int NumPendingAcks, desc="num acks expected"; 17910210Sandreas.hansson@arm.com MachineID OriginalRequestor, desc="Original Requestor"; 1809243SN/A MachineID WTRequestor, desc="WT Requestor"; 1819243SN/A bool Cached, desc="data hit in Cache"; 1829243SN/A bool MemData, desc="Got MemData?",default="false"; 1839243SN/A bool wtData, desc="Got write through data?",default="false"; 1849243SN/A bool atomicData, desc="Got Atomic op?",default="false"; 1859243SN/A Cycles InitialRequestTime, desc="..."; 18610207Sandreas.hansson@arm.com Cycles ForwardRequestTime, desc="..."; 1879243SN/A Cycles ProbeRequestStartTime, desc="..."; 1889243SN/A bool DemandRequest, desc="for profiling"; 18910246Sandreas.hansson@arm.com MachineID LastSender, desc="Mach which this block came from"; 19010394Swendy.elsasser@arm.com bool L3Hit, default="false", desc="Was this an L3 hit?"; 1919243SN/A bool TriggeredAcksComplete, default="false", desc="True if already triggered acks complete"; 19210211Sandreas.hansson@arm.com WriteMask writeMask, desc="outstanding write through mask"; 19310210Sandreas.hansson@arm.com } 1949969SN/A 1959243SN/A structure(TBETable, external="yes") { 19610141SN/A TBE lookup(Addr); 1979727SN/A void allocate(Addr); 1989727SN/A void deallocate(Addr); 1999727SN/A bool isPresent(Addr); 20010618SOmar.Naji@arm.com } 20110246Sandreas.hansson@arm.com 20210141SN/A TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs"; 2039243SN/A 2049243SN/A Tick clockEdge(); 2059243SN/A Tick cyclesToTicks(Cycles c); 20610618SOmar.Naji@arm.com 20710618SOmar.Naji@arm.com void set_tbe(TBE a); 20811678Swendy.elsasser@arm.com void unset_tbe(); 20911678Swendy.elsasser@arm.com void wakeUpAllBuffers(); 21011678Swendy.elsasser@arm.com void wakeUpBuffers(Addr a); 21111678Swendy.elsasser@arm.com Cycles curCycle(); 21211678Swendy.elsasser@arm.com 21311678Swendy.elsasser@arm.com MachineID mapAddressToMachine(Addr addr, MachineType mtype); 21411678Swendy.elsasser@arm.com 21511678Swendy.elsasser@arm.com Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" { 21611678Swendy.elsasser@arm.com Entry dir_entry := static_cast(Entry, "pointer", directory.lookup(addr)); 21711678Swendy.elsasser@arm.com 21811678Swendy.elsasser@arm.com if (is_valid(dir_entry)) { 21911678Swendy.elsasser@arm.com //DPRINTF(RubySlicc, "Getting entry %s: %s\n", addr, dir_entry.DataBlk); 22011678Swendy.elsasser@arm.com return dir_entry; 22111678Swendy.elsasser@arm.com } 22211678Swendy.elsasser@arm.com 22311678Swendy.elsasser@arm.com dir_entry := static_cast(Entry, "pointer", 22411678Swendy.elsasser@arm.com directory.allocate(addr, new Entry)); 22511678Swendy.elsasser@arm.com return dir_entry; 22611678Swendy.elsasser@arm.com } 22711678Swendy.elsasser@arm.com 22811678Swendy.elsasser@arm.com DataBlock getDataBlock(Addr addr), return_by_ref="yes" { 22911678Swendy.elsasser@arm.com TBE tbe := TBEs.lookup(addr); 23011678Swendy.elsasser@arm.com if (is_valid(tbe) && tbe.MemData) { 23111678Swendy.elsasser@arm.com DPRINTF(RubySlicc, "Returning DataBlk from TBE %s:%s\n", addr, tbe); 23211678Swendy.elsasser@arm.com return tbe.DataBlk; 23311678Swendy.elsasser@arm.com } 23411678Swendy.elsasser@arm.com DPRINTF(RubySlicc, "Returning DataBlk from Dir %s:%s\n", addr, getDirectoryEntry(addr)); 23511678Swendy.elsasser@arm.com return getDirectoryEntry(addr).DataBlk; 23611678Swendy.elsasser@arm.com } 23711678Swendy.elsasser@arm.com 23811678Swendy.elsasser@arm.com State getState(TBE tbe, CacheEntry entry, Addr addr) { 23911678Swendy.elsasser@arm.com return getDirectoryEntry(addr).DirectoryState; 24011678Swendy.elsasser@arm.com } 24111678Swendy.elsasser@arm.com 24211678Swendy.elsasser@arm.com State getStateFromAddr(Addr addr) { 24311678Swendy.elsasser@arm.com return getDirectoryEntry(addr).DirectoryState; 24411678Swendy.elsasser@arm.com } 24511678Swendy.elsasser@arm.com 24611678Swendy.elsasser@arm.com void setState(TBE tbe, CacheEntry entry, Addr addr, State state) { 24711678Swendy.elsasser@arm.com getDirectoryEntry(addr).DirectoryState := state; 24811678Swendy.elsasser@arm.com } 24911678Swendy.elsasser@arm.com 25011678Swendy.elsasser@arm.com AccessPermission getAccessPermission(Addr addr) { 25111678Swendy.elsasser@arm.com // For this Directory, all permissions are just tracked in Directory, since 25211678Swendy.elsasser@arm.com // it's not possible to have something in TBE but not Dir, just keep track 25311678Swendy.elsasser@arm.com // of state all in one place. 25411678Swendy.elsasser@arm.com if(directory.isPresent(addr)) { 25511678Swendy.elsasser@arm.com return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState); 25611678Swendy.elsasser@arm.com } 25711678Swendy.elsasser@arm.com 25811678Swendy.elsasser@arm.com return AccessPermission:NotPresent; 25911678Swendy.elsasser@arm.com } 26011678Swendy.elsasser@arm.com 26111678Swendy.elsasser@arm.com void functionalRead(Addr addr, Packet *pkt) { 26211678Swendy.elsasser@arm.com TBE tbe := TBEs.lookup(addr); 26311678Swendy.elsasser@arm.com if(is_valid(tbe)) { 26411678Swendy.elsasser@arm.com testAndRead(addr, tbe.DataBlk, pkt); 26511678Swendy.elsasser@arm.com } else { 26611678Swendy.elsasser@arm.com functionalMemoryRead(pkt); 26711678Swendy.elsasser@arm.com } 26811678Swendy.elsasser@arm.com } 26911678Swendy.elsasser@arm.com 27011678Swendy.elsasser@arm.com int functionalWrite(Addr addr, Packet *pkt) { 27111678Swendy.elsasser@arm.com int num_functional_writes := 0; 27211678Swendy.elsasser@arm.com 27311678Swendy.elsasser@arm.com TBE tbe := TBEs.lookup(addr); 27411678Swendy.elsasser@arm.com if(is_valid(tbe)) { 27511678Swendy.elsasser@arm.com num_functional_writes := num_functional_writes + 27611678Swendy.elsasser@arm.com testAndWrite(addr, tbe.DataBlk, pkt); 27711678Swendy.elsasser@arm.com } 27811678Swendy.elsasser@arm.com 27911678Swendy.elsasser@arm.com num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt); 28011678Swendy.elsasser@arm.com return num_functional_writes; 28111678Swendy.elsasser@arm.com } 28211678Swendy.elsasser@arm.com 28311678Swendy.elsasser@arm.com void setAccessPermission(CacheEntry entry, Addr addr, State state) { 28410618SOmar.Naji@arm.com getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state)); 28510618SOmar.Naji@arm.com } 28610618SOmar.Naji@arm.com 28710618SOmar.Naji@arm.com void recordRequestType(RequestType request_type, Addr addr) { 28810618SOmar.Naji@arm.com if (request_type == RequestType:L3DataArrayRead) { 28910618SOmar.Naji@arm.com L3CacheMemory.recordRequestType(CacheRequestType:DataArrayRead, addr); 29010618SOmar.Naji@arm.com } else if (request_type == RequestType:L3DataArrayWrite) { 29110618SOmar.Naji@arm.com L3CacheMemory.recordRequestType(CacheRequestType:DataArrayWrite, addr); 29210618SOmar.Naji@arm.com } else if (request_type == RequestType:L3TagArrayRead) { 29310618SOmar.Naji@arm.com L3CacheMemory.recordRequestType(CacheRequestType:TagArrayRead, addr); 29410618SOmar.Naji@arm.com } else if (request_type == RequestType:L3TagArrayWrite) { 29510618SOmar.Naji@arm.com L3CacheMemory.recordRequestType(CacheRequestType:TagArrayWrite, addr); 29610618SOmar.Naji@arm.com } 29710618SOmar.Naji@arm.com } 29810618SOmar.Naji@arm.com 29910618SOmar.Naji@arm.com bool checkResourceAvailable(RequestType request_type, Addr addr) { 30010618SOmar.Naji@arm.com if (request_type == RequestType:L3DataArrayRead) { 30110618SOmar.Naji@arm.com return L3CacheMemory.checkResourceAvailable(CacheResourceType:DataArray, addr); 30211678Swendy.elsasser@arm.com } else if (request_type == RequestType:L3DataArrayWrite) { 30310618SOmar.Naji@arm.com return L3CacheMemory.checkResourceAvailable(CacheResourceType:DataArray, addr); 30410618SOmar.Naji@arm.com } else if (request_type == RequestType:L3TagArrayRead) { 30510618SOmar.Naji@arm.com return L3CacheMemory.checkResourceAvailable(CacheResourceType:TagArray, addr); 30610618SOmar.Naji@arm.com } else if (request_type == RequestType:L3TagArrayWrite) { 30711678Swendy.elsasser@arm.com return L3CacheMemory.checkResourceAvailable(CacheResourceType:TagArray, addr); 30810618SOmar.Naji@arm.com } else { 30911678Swendy.elsasser@arm.com error("Invalid RequestType type in checkResourceAvailable"); 31010618SOmar.Naji@arm.com return true; 31110618SOmar.Naji@arm.com } 31210618SOmar.Naji@arm.com } 31310618SOmar.Naji@arm.com 31410618SOmar.Naji@arm.com // ** OUT_PORTS ** 31510618SOmar.Naji@arm.com out_port(probeNetwork_out, NBProbeRequestMsg, probeToCore); 31610618SOmar.Naji@arm.com out_port(responseNetwork_out, ResponseMsg, responseToCore); 31710618SOmar.Naji@arm.com 31810618SOmar.Naji@arm.com out_port(requestNetworkReg_out, CPURequestMsg, reqToRegDir); 31910618SOmar.Naji@arm.com out_port(regAckNetwork_out, UnblockMsg, unblockToRegDir); 32010618SOmar.Naji@arm.com 32110618SOmar.Naji@arm.com out_port(triggerQueue_out, TriggerMsg, triggerQueue); 32210618SOmar.Naji@arm.com out_port(L3TriggerQueue_out, TriggerMsg, L3triggerQueue); 32310618SOmar.Naji@arm.com 32410618SOmar.Naji@arm.com // ** IN_PORTS ** 32510618SOmar.Naji@arm.com 32610618SOmar.Naji@arm.com // Trigger Queue 32710618SOmar.Naji@arm.com in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=7) { 32810618SOmar.Naji@arm.com if (triggerQueue_in.isReady(clockEdge())) { 32910618SOmar.Naji@arm.com peek(triggerQueue_in, TriggerMsg) { 33010618SOmar.Naji@arm.com TBE tbe := TBEs.lookup(in_msg.addr); 33110618SOmar.Naji@arm.com CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(in_msg.addr)); 33210618SOmar.Naji@arm.com if (in_msg.Type == TriggerType:AcksComplete) { 33310618SOmar.Naji@arm.com trigger(Event:ProbeAcksComplete, in_msg.addr, entry, tbe); 33410618SOmar.Naji@arm.com } else if (in_msg.Type == TriggerType:UnblockWriteThrough) { 33510618SOmar.Naji@arm.com trigger(Event:UnblockWriteThrough, in_msg.addr, entry, tbe); 33610618SOmar.Naji@arm.com } else { 33710618SOmar.Naji@arm.com error("Unknown trigger msg"); 33810618SOmar.Naji@arm.com } 33910618SOmar.Naji@arm.com } 34011678Swendy.elsasser@arm.com } 34111678Swendy.elsasser@arm.com } 34211678Swendy.elsasser@arm.com 34311678Swendy.elsasser@arm.com in_port(L3TriggerQueue_in, TriggerMsg, L3triggerQueue, rank=6) { 34411678Swendy.elsasser@arm.com if (L3TriggerQueue_in.isReady(clockEdge())) { 34511678Swendy.elsasser@arm.com peek(L3TriggerQueue_in, TriggerMsg) { 34611678Swendy.elsasser@arm.com TBE tbe := TBEs.lookup(in_msg.addr); 34711678Swendy.elsasser@arm.com CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(in_msg.addr)); 34811678Swendy.elsasser@arm.com if (in_msg.Type == TriggerType:L3Hit) { 34911678Swendy.elsasser@arm.com trigger(Event:L3Hit, in_msg.addr, entry, tbe); 35011678Swendy.elsasser@arm.com } else { 35111678Swendy.elsasser@arm.com error("Unknown trigger msg"); 35211678Swendy.elsasser@arm.com } 35311678Swendy.elsasser@arm.com } 35411678Swendy.elsasser@arm.com } 35510618SOmar.Naji@arm.com } 35610618SOmar.Naji@arm.com 35710618SOmar.Naji@arm.com // Unblock Network 35810618SOmar.Naji@arm.com in_port(unblockNetwork_in, UnblockMsg, unblockFromCores, rank=5) { 35911678Swendy.elsasser@arm.com if (unblockNetwork_in.isReady(clockEdge())) { 36011678Swendy.elsasser@arm.com peek(unblockNetwork_in, UnblockMsg) { 36111678Swendy.elsasser@arm.com TBE tbe := TBEs.lookup(in_msg.addr); 36211678Swendy.elsasser@arm.com CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(in_msg.addr)); 36311678Swendy.elsasser@arm.com trigger(Event:CoreUnblock, in_msg.addr, entry, tbe); 36411678Swendy.elsasser@arm.com } 36510618SOmar.Naji@arm.com } 36610618SOmar.Naji@arm.com } 36710618SOmar.Naji@arm.com 36810618SOmar.Naji@arm.com // Core response network 36910618SOmar.Naji@arm.com in_port(responseNetwork_in, ResponseMsg, responseFromCores, rank=4) { 37010618SOmar.Naji@arm.com if (responseNetwork_in.isReady(clockEdge())) { 37110618SOmar.Naji@arm.com peek(responseNetwork_in, ResponseMsg) { 37210618SOmar.Naji@arm.com DPRINTF(RubySlicc, "core responses %s\n", in_msg); 37310618SOmar.Naji@arm.com TBE tbe := TBEs.lookup(in_msg.addr); 37410618SOmar.Naji@arm.com CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(in_msg.addr)); 37510618SOmar.Naji@arm.com if (in_msg.Type == CoherenceResponseType:CPUPrbResp) { 37610618SOmar.Naji@arm.com if (is_valid(tbe) && tbe.NumPendingAcks == 1 37710618SOmar.Naji@arm.com && tbe.TriggeredAcksComplete == false) { 37810618SOmar.Naji@arm.com trigger(Event:LastCPUPrbResp, in_msg.addr, entry, tbe); 37910618SOmar.Naji@arm.com } else { 38010618SOmar.Naji@arm.com trigger(Event:CPUPrbResp, in_msg.addr, entry, tbe); 38110618SOmar.Naji@arm.com } 38210618SOmar.Naji@arm.com } else if (in_msg.Type == CoherenceResponseType:CPUData) { 38310618SOmar.Naji@arm.com trigger(Event:CPUData, in_msg.addr, entry, tbe); 38410618SOmar.Naji@arm.com } else if (in_msg.Type == CoherenceResponseType:StaleNotif) { 38510618SOmar.Naji@arm.com trigger(Event:StaleWB, in_msg.addr, entry, tbe); 38611678Swendy.elsasser@arm.com } else { 38711678Swendy.elsasser@arm.com error("Unexpected response type"); 38811678Swendy.elsasser@arm.com } 38911678Swendy.elsasser@arm.com } 39011678Swendy.elsasser@arm.com } 39111678Swendy.elsasser@arm.com } 39211678Swendy.elsasser@arm.com 39311678Swendy.elsasser@arm.com // off-chip memory request/response is done 39411678Swendy.elsasser@arm.com in_port(memQueue_in, MemoryMsg, responseFromMemory, rank=3) { 39511678Swendy.elsasser@arm.com if (memQueue_in.isReady(clockEdge())) { 39611678Swendy.elsasser@arm.com peek(memQueue_in, MemoryMsg) { 39711678Swendy.elsasser@arm.com TBE tbe := TBEs.lookup(in_msg.addr); 39811678Swendy.elsasser@arm.com CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(in_msg.addr)); 39911678Swendy.elsasser@arm.com if (in_msg.Type == MemoryRequestType:MEMORY_READ) { 40011678Swendy.elsasser@arm.com trigger(Event:MemData, in_msg.addr, entry, tbe); 40110618SOmar.Naji@arm.com DPRINTF(RubySlicc, "%s\n", in_msg); 40210618SOmar.Naji@arm.com } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) { 40310618SOmar.Naji@arm.com trigger(Event:WBAck, in_msg.addr, entry, tbe); // ignore WBAcks, don't care about them. 40410618SOmar.Naji@arm.com } else { 40511678Swendy.elsasser@arm.com DPRINTF(RubySlicc, "%s\n", in_msg.Type); 40611678Swendy.elsasser@arm.com error("Invalid message"); 40711678Swendy.elsasser@arm.com } 40811678Swendy.elsasser@arm.com } 40911678Swendy.elsasser@arm.com } 41011678Swendy.elsasser@arm.com } 41111678Swendy.elsasser@arm.com 41211678Swendy.elsasser@arm.com in_port(regBuf_in, CPURequestMsg, reqFromRegBuf, rank=2) { 41311678Swendy.elsasser@arm.com if (regBuf_in.isReady(clockEdge())) { 41411678Swendy.elsasser@arm.com peek(regBuf_in, CPURequestMsg) { 41511678Swendy.elsasser@arm.com TBE tbe := TBEs.lookup(in_msg.addr); 41611678Swendy.elsasser@arm.com CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(in_msg.addr)); 41711678Swendy.elsasser@arm.com if (in_msg.Type == CoherenceRequestType:ForceInv) { 41811678Swendy.elsasser@arm.com trigger(Event:Inv, in_msg.addr, entry, tbe); 41911678Swendy.elsasser@arm.com } else if (in_msg.Type == CoherenceRequestType:ForceDowngrade) { 42011678Swendy.elsasser@arm.com trigger(Event:Downgrade, in_msg.addr, entry, tbe); 42111678Swendy.elsasser@arm.com } else { 42211678Swendy.elsasser@arm.com error("Bad request from region buffer"); 42311678Swendy.elsasser@arm.com } 42411678Swendy.elsasser@arm.com } 42511678Swendy.elsasser@arm.com } 42611678Swendy.elsasser@arm.com } 42710618SOmar.Naji@arm.com 42810618SOmar.Naji@arm.com in_port(regDir_in, CPURequestMsg, reqFromRegDir, rank=1) { 42910618SOmar.Naji@arm.com if (regDir_in.isReady(clockEdge())) { 43010618SOmar.Naji@arm.com peek(regDir_in, CPURequestMsg) { 43110618SOmar.Naji@arm.com TBE tbe := TBEs.lookup(in_msg.addr); 43210618SOmar.Naji@arm.com CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(in_msg.addr)); 43311675Swendy.elsasser@arm.com if (in_msg.Type == CoherenceRequestType:RdBlk) { 43411675Swendy.elsasser@arm.com trigger(Event:RdBlk, in_msg.addr, entry, tbe); 43511675Swendy.elsasser@arm.com } else if (in_msg.Type == CoherenceRequestType:RdBlkS) { 43611675Swendy.elsasser@arm.com trigger(Event:RdBlkS, in_msg.addr, entry, tbe); 43711675Swendy.elsasser@arm.com } else if (in_msg.Type == CoherenceRequestType:RdBlkM) { 43811675Swendy.elsasser@arm.com trigger(Event:RdBlkM, in_msg.addr, entry, tbe); 43911675Swendy.elsasser@arm.com } else if (in_msg.Type == CoherenceRequestType:Atomic) { 44011675Swendy.elsasser@arm.com trigger(Event:Atomic, in_msg.addr, entry, tbe); 44110618SOmar.Naji@arm.com } else if (in_msg.Type == CoherenceRequestType:WriteThrough) { 44210618SOmar.Naji@arm.com trigger(Event:WriteThrough, in_msg.addr, entry, tbe); 44310618SOmar.Naji@arm.com } else if (in_msg.Type == CoherenceRequestType:VicDirty) { 44410618SOmar.Naji@arm.com if (getDirectoryEntry(in_msg.addr).VicDirtyIgnore.isElement(in_msg.Requestor)) { 44510618SOmar.Naji@arm.com DPRINTF(RubySlicc, "Dropping VicDirty for address %s\n", in_msg.addr); 44610618SOmar.Naji@arm.com trigger(Event:StaleVicDirty, in_msg.addr, entry, tbe); 44710618SOmar.Naji@arm.com } else { 44810618SOmar.Naji@arm.com trigger(Event:VicDirty, in_msg.addr, entry, tbe); 44910618SOmar.Naji@arm.com } 45010618SOmar.Naji@arm.com } else if (in_msg.Type == CoherenceRequestType:VicClean) { 45110618SOmar.Naji@arm.com if (getDirectoryEntry(in_msg.addr).VicDirtyIgnore.isElement(in_msg.Requestor)) { 45210618SOmar.Naji@arm.com DPRINTF(RubySlicc, "Dropping VicClean for address %s\n", in_msg.addr); 45310618SOmar.Naji@arm.com trigger(Event:StaleVicDirty, in_msg.addr, entry, tbe); 45410618SOmar.Naji@arm.com } else { 45512081Sspwilson2@wisc.edu trigger(Event:VicClean, in_msg.addr, entry, tbe); 45610618SOmar.Naji@arm.com } 45710618SOmar.Naji@arm.com } else { 45810618SOmar.Naji@arm.com error("Bad message type fwded from Region Dir"); 45910618SOmar.Naji@arm.com } 46010618SOmar.Naji@arm.com } 46110618SOmar.Naji@arm.com } 46210618SOmar.Naji@arm.com } 46310618SOmar.Naji@arm.com 46410618SOmar.Naji@arm.com in_port(requestNetwork_in, CPURequestMsg, requestFromCores, rank=0) { 46510618SOmar.Naji@arm.com if (requestNetwork_in.isReady(clockEdge())) { 46610618SOmar.Naji@arm.com peek(requestNetwork_in, CPURequestMsg) { 46710618SOmar.Naji@arm.com TBE tbe := TBEs.lookup(in_msg.addr); 46810618SOmar.Naji@arm.com CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(in_msg.addr)); 46910618SOmar.Naji@arm.com if (in_msg.Private) { 47010618SOmar.Naji@arm.com // Bypass the region dir 47110619Sandreas.hansson@arm.com if (in_msg.Type == CoherenceRequestType:RdBlk) { 47210619Sandreas.hansson@arm.com trigger(Event:RdBlkP, in_msg.addr, entry, tbe); 47310619Sandreas.hansson@arm.com } else if (in_msg.Type == CoherenceRequestType:RdBlkS) { 47410619Sandreas.hansson@arm.com trigger(Event:RdBlkSP, in_msg.addr, entry, tbe); 47510619Sandreas.hansson@arm.com } else if (in_msg.Type == CoherenceRequestType:RdBlkM) { 47612266Sradhika.jagtap@arm.com trigger(Event:RdBlkMP, in_msg.addr, entry, tbe); 47712266Sradhika.jagtap@arm.com } else if (in_msg.Type == CoherenceRequestType:Atomic) { 47810618SOmar.Naji@arm.com trigger(Event:AtomicP, in_msg.addr, entry, tbe); 47910618SOmar.Naji@arm.com } else if (in_msg.Type == CoherenceRequestType:WriteThrough) { 48010618SOmar.Naji@arm.com trigger(Event:WriteThroughP, in_msg.addr, entry, tbe); 48112266Sradhika.jagtap@arm.com } else if (in_msg.Type == CoherenceRequestType:VicDirty) { 48210618SOmar.Naji@arm.com if (getDirectoryEntry(in_msg.addr).VicDirtyIgnore.isElement(in_msg.Requestor)) { 48310618SOmar.Naji@arm.com DPRINTF(RubySlicc, "Dropping VicDirtyP for address %s\n", in_msg.addr); 48411676Swendy.elsasser@arm.com trigger(Event:StaleVicDirtyP, in_msg.addr, entry, tbe); 48511676Swendy.elsasser@arm.com } else { 48611676Swendy.elsasser@arm.com DPRINTF(RubySlicc, "Got VicDirty from %s on %s\n", in_msg.Requestor, in_msg.addr); 48711676Swendy.elsasser@arm.com trigger(Event:VicDirtyP, in_msg.addr, entry, tbe); 48811676Swendy.elsasser@arm.com } 48911676Swendy.elsasser@arm.com } else if (in_msg.Type == CoherenceRequestType:VicClean) { 49011676Swendy.elsasser@arm.com if (getDirectoryEntry(in_msg.addr).VicDirtyIgnore.isElement(in_msg.Requestor)) { 49111676Swendy.elsasser@arm.com DPRINTF(RubySlicc, "Dropping VicCleanP for address %s\n", in_msg.addr); 49211676Swendy.elsasser@arm.com trigger(Event:StaleVicDirtyP, in_msg.addr, entry, tbe); 49311678Swendy.elsasser@arm.com } else { 49411678Swendy.elsasser@arm.com DPRINTF(RubySlicc, "Got VicClean from %s on %s\n", in_msg.Requestor, in_msg.addr); 49511678Swendy.elsasser@arm.com trigger(Event:VicCleanP, in_msg.addr, entry, tbe); 49611678Swendy.elsasser@arm.com } 49711678Swendy.elsasser@arm.com } else { 49811678Swendy.elsasser@arm.com error("Bad message type for private access"); 49911678Swendy.elsasser@arm.com } 50011678Swendy.elsasser@arm.com } else { 50111678Swendy.elsasser@arm.com trigger(Event:CPUReq, in_msg.addr, entry, tbe); 50211678Swendy.elsasser@arm.com } 50311678Swendy.elsasser@arm.com } 50411678Swendy.elsasser@arm.com } 50511678Swendy.elsasser@arm.com } 50611678Swendy.elsasser@arm.com 50711678Swendy.elsasser@arm.com // Actions 50811678Swendy.elsasser@arm.com action(s_sendResponseS, "s", desc="send Shared response") { 50911678Swendy.elsasser@arm.com enqueue(responseNetwork_out, ResponseMsg, response_latency) { 51011678Swendy.elsasser@arm.com out_msg.addr := address; 51111678Swendy.elsasser@arm.com out_msg.Type := CoherenceResponseType:NBSysResp; 51211678Swendy.elsasser@arm.com if (tbe.L3Hit) { 51311678Swendy.elsasser@arm.com out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0)); 51411678Swendy.elsasser@arm.com } else { 51511678Swendy.elsasser@arm.com out_msg.Sender := machineID; 51610618SOmar.Naji@arm.com } 51710618SOmar.Naji@arm.com out_msg.Destination.add(tbe.OriginalRequestor); 51810618SOmar.Naji@arm.com out_msg.DataBlk := tbe.DataBlk; 51910618SOmar.Naji@arm.com out_msg.MessageSize := MessageSizeType:Response_Data; 52010618SOmar.Naji@arm.com out_msg.Dirty := false; 52111675Swendy.elsasser@arm.com out_msg.State := CoherenceState:Shared; 52211675Swendy.elsasser@arm.com out_msg.InitialRequestTime := tbe.InitialRequestTime; 52311675Swendy.elsasser@arm.com out_msg.ForwardRequestTime := tbe.ForwardRequestTime; 52411675Swendy.elsasser@arm.com out_msg.ProbeRequestStartTime := tbe.ProbeRequestStartTime; 52511675Swendy.elsasser@arm.com out_msg.OriginalResponder := tbe.LastSender; 52611675Swendy.elsasser@arm.com out_msg.DemandRequest := tbe.DemandRequest; 52711675Swendy.elsasser@arm.com out_msg.L3Hit := tbe.L3Hit; 52811675Swendy.elsasser@arm.com DPRINTF(RubySlicc, "%s\n", out_msg); 52910618SOmar.Naji@arm.com } 53010618SOmar.Naji@arm.com } 53110618SOmar.Naji@arm.com 53210618SOmar.Naji@arm.com action(es_sendResponseES, "es", desc="send Exclusive or Shared response") { 53310618SOmar.Naji@arm.com enqueue(responseNetwork_out, ResponseMsg, response_latency) { 53411677Swendy.elsasser@arm.com out_msg.addr := address; 53511677Swendy.elsasser@arm.com out_msg.Type := CoherenceResponseType:NBSysResp; 53611677Swendy.elsasser@arm.com if (tbe.L3Hit) { 53711677Swendy.elsasser@arm.com out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0)); 53811677Swendy.elsasser@arm.com } else { 53911678Swendy.elsasser@arm.com out_msg.Sender := machineID; 54012266Sradhika.jagtap@arm.com } 54112266Sradhika.jagtap@arm.com out_msg.Destination.add(tbe.OriginalRequestor); 54212266Sradhika.jagtap@arm.com out_msg.DataBlk := tbe.DataBlk; 54312266Sradhika.jagtap@arm.com out_msg.MessageSize := MessageSizeType:Response_Data; 54412266Sradhika.jagtap@arm.com out_msg.Dirty := tbe.Dirty; 54511678Swendy.elsasser@arm.com if (tbe.Cached) { 54611678Swendy.elsasser@arm.com out_msg.State := CoherenceState:Shared; 54711678Swendy.elsasser@arm.com } else { 54811678Swendy.elsasser@arm.com out_msg.State := CoherenceState:Exclusive; 54911678Swendy.elsasser@arm.com } 55011678Swendy.elsasser@arm.com out_msg.InitialRequestTime := tbe.InitialRequestTime; 55111678Swendy.elsasser@arm.com out_msg.ForwardRequestTime := tbe.ForwardRequestTime; 55211678Swendy.elsasser@arm.com out_msg.ProbeRequestStartTime := tbe.ProbeRequestStartTime; 55311678Swendy.elsasser@arm.com out_msg.OriginalResponder := tbe.LastSender; 55411678Swendy.elsasser@arm.com out_msg.DemandRequest := tbe.DemandRequest; 55511678Swendy.elsasser@arm.com out_msg.L3Hit := tbe.L3Hit; 55611678Swendy.elsasser@arm.com DPRINTF(RubySlicc, "%s\n", out_msg); 55711678Swendy.elsasser@arm.com } 55811678Swendy.elsasser@arm.com } 55911678Swendy.elsasser@arm.com 56011678Swendy.elsasser@arm.com action(m_sendResponseM, "m", desc="send Modified response") { 56111678Swendy.elsasser@arm.com if (tbe.wtData) { 56212084Sspwilson2@wisc.edu enqueue(triggerQueue_out, TriggerMsg, 1) { 56311678Swendy.elsasser@arm.com out_msg.addr := address; 56410618SOmar.Naji@arm.com out_msg.Type := TriggerType:UnblockWriteThrough; 56512084Sspwilson2@wisc.edu } 56610618SOmar.Naji@arm.com } else { 56710618SOmar.Naji@arm.com enqueue(responseNetwork_out, ResponseMsg, response_latency) { 56812084Sspwilson2@wisc.edu out_msg.addr := address; 56910618SOmar.Naji@arm.com out_msg.Type := CoherenceResponseType:NBSysResp; 57010618SOmar.Naji@arm.com if (tbe.L3Hit) { 57112084Sspwilson2@wisc.edu out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0)); 57210618SOmar.Naji@arm.com } else { 57310618SOmar.Naji@arm.com out_msg.Sender := machineID; 57412084Sspwilson2@wisc.edu } 57510618SOmar.Naji@arm.com out_msg.Destination.add(tbe.OriginalRequestor); 57611678Swendy.elsasser@arm.com out_msg.DataBlk := tbe.DataBlk; 57712084Sspwilson2@wisc.edu out_msg.MessageSize := MessageSizeType:Response_Data; 57811678Swendy.elsasser@arm.com out_msg.Dirty := tbe.Dirty; 57910618SOmar.Naji@arm.com out_msg.State := CoherenceState:Modified; 58010618SOmar.Naji@arm.com out_msg.CtoD := false; 58112266Sradhika.jagtap@arm.com out_msg.InitialRequestTime := tbe.InitialRequestTime; 58212266Sradhika.jagtap@arm.com out_msg.ForwardRequestTime := tbe.ForwardRequestTime; 58312266Sradhika.jagtap@arm.com out_msg.ProbeRequestStartTime := tbe.ProbeRequestStartTime; 58412266Sradhika.jagtap@arm.com out_msg.OriginalResponder := tbe.LastSender; 58512266Sradhika.jagtap@arm.com out_msg.DemandRequest := tbe.DemandRequest; 58612266Sradhika.jagtap@arm.com out_msg.L3Hit := tbe.L3Hit; 58711677Swendy.elsasser@arm.com if (tbe.atomicData) { 58811677Swendy.elsasser@arm.com out_msg.WTRequestor := tbe.WTRequestor; 58911677Swendy.elsasser@arm.com } 59011677Swendy.elsasser@arm.com DPRINTF(RubySlicc, "%s\n", out_msg); 59111677Swendy.elsasser@arm.com } 59211677Swendy.elsasser@arm.com if (tbe.atomicData) { 59311677Swendy.elsasser@arm.com enqueue(triggerQueue_out, TriggerMsg, 1) { 59411677Swendy.elsasser@arm.com out_msg.addr := address; 59512266Sradhika.jagtap@arm.com out_msg.Type := TriggerType:UnblockWriteThrough; 59612266Sradhika.jagtap@arm.com } 59712266Sradhika.jagtap@arm.com } 59812266Sradhika.jagtap@arm.com } 59912266Sradhika.jagtap@arm.com } 60012266Sradhika.jagtap@arm.com 60112266Sradhika.jagtap@arm.com action(sb_sendResponseSBypass, "sb", desc="send Shared response") { 60212266Sradhika.jagtap@arm.com peek(requestNetwork_in, CPURequestMsg) { 60312266Sradhika.jagtap@arm.com enqueue(responseNetwork_out, ResponseMsg, response_latency) { 60412266Sradhika.jagtap@arm.com out_msg.addr := address; 60512266Sradhika.jagtap@arm.com out_msg.Type := CoherenceResponseType:NBSysResp; 60612266Sradhika.jagtap@arm.com if (tbe.L3Hit) { 60712266Sradhika.jagtap@arm.com out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0)); 60812266Sradhika.jagtap@arm.com } else { 60912266Sradhika.jagtap@arm.com out_msg.Sender := machineID; 61012266Sradhika.jagtap@arm.com } 61112266Sradhika.jagtap@arm.com out_msg.Destination.add(in_msg.Requestor); 61212266Sradhika.jagtap@arm.com out_msg.DataBlk := tbe.DataBlk; 61312266Sradhika.jagtap@arm.com out_msg.MessageSize := MessageSizeType:Response_Data; 61412266Sradhika.jagtap@arm.com out_msg.Dirty := false; 61512266Sradhika.jagtap@arm.com out_msg.State := CoherenceState:Shared; 61612266Sradhika.jagtap@arm.com out_msg.InitialRequestTime := in_msg.InitialRequestTime; 61712266Sradhika.jagtap@arm.com out_msg.ForwardRequestTime := curCycle(); 61812266Sradhika.jagtap@arm.com out_msg.ProbeRequestStartTime := in_msg.ProbeRequestStartTime; 6199243SN/A out_msg.OriginalResponder := tbe.LastSender; 6209831SN/A out_msg.DemandRequest := false; 6219831SN/A out_msg.L3Hit := tbe.L3Hit; 6229831SN/A DPRINTF(RubySlicc, "%s\n", out_msg); 6239831SN/A } 6249831SN/A } 6259831SN/A } 6269831SN/A 6279831SN/A action(esb_sendResponseESBypass, "esb", desc="send Exclusive or Shared response") { 6289831SN/A peek(requestNetwork_in, CPURequestMsg) { 6299831SN/A enqueue(responseNetwork_out, ResponseMsg, response_latency) { 6309831SN/A out_msg.addr := address; 6319831SN/A out_msg.Type := CoherenceResponseType:NBSysResp; 6329831SN/A if (tbe.L3Hit) { 6339831SN/A out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0)); 6349831SN/A } else { 6359831SN/A out_msg.Sender := machineID; 6369831SN/A } 63710618SOmar.Naji@arm.com out_msg.Destination.add(in_msg.Requestor); 6389831SN/A out_msg.DataBlk := tbe.DataBlk; 6399831SN/A out_msg.MessageSize := MessageSizeType:Response_Data; 6409831SN/A out_msg.Dirty := tbe.Dirty; 6419243SN/A if (tbe.Cached || in_msg.ForceShared) { 6429243SN/A out_msg.State := CoherenceState:Shared; 6439243SN/A } else { 6449243SN/A out_msg.State := CoherenceState:Exclusive; 6459243SN/A } 6469243SN/A out_msg.InitialRequestTime := in_msg.InitialRequestTime; 6479243SN/A out_msg.ForwardRequestTime := curCycle(); 6489243SN/A out_msg.ProbeRequestStartTime := in_msg.ProbeRequestStartTime; 6499243SN/A out_msg.OriginalResponder := tbe.LastSender; 6509243SN/A out_msg.DemandRequest := false; 6519243SN/A out_msg.L3Hit := tbe.L3Hit; 6529243SN/A DPRINTF(RubySlicc, "%s\n", out_msg); 6539243SN/A } 6549243SN/A } 6559243SN/A } 6569243SN/A 6579966SN/A action(mbwt_sendResponseWriteThroughBypass, "mbwt", desc="send write through response") { 6589966SN/A peek(requestNetwork_in, CPURequestMsg) { 6599243SN/A if (in_msg.Type == CoherenceRequestType:WriteThrough) { 6609243SN/A enqueue(responseNetwork_out, ResponseMsg, response_latency) { 6619967SN/A out_msg.addr := address; 66210245Sandreas.hansson@arm.com out_msg.Type := CoherenceResponseType:NBSysWBAck; 6639831SN/A out_msg.Destination.add(in_msg.Requestor); 6649831SN/A out_msg.WTRequestor := in_msg.WTRequestor; 6659967SN/A out_msg.Sender := machineID; 6669967SN/A out_msg.MessageSize := MessageSizeType:Writeback_Control; 6679967SN/A out_msg.InitialRequestTime := in_msg.InitialRequestTime; 6689967SN/A out_msg.ForwardRequestTime := curCycle(); 6699967SN/A out_msg.ProbeRequestStartTime := in_msg.ProbeRequestStartTime; 6709967SN/A out_msg.DemandRequest := false; 6719967SN/A } 6729831SN/A } else { 6739831SN/A assert(in_msg.Type == CoherenceRequestType:Atomic); 6749831SN/A enqueue(responseNetwork_out, ResponseMsg, response_latency) { 6759831SN/A out_msg.addr := address; 6769831SN/A out_msg.Type := CoherenceResponseType:NBSysResp; 6779832SN/A if (tbe.L3Hit) { 6789831SN/A out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0)); 6799831SN/A } else { 6809831SN/A out_msg.Sender := machineID; 6819831SN/A } 6829831SN/A out_msg.Destination.add(in_msg.Requestor); 6839832SN/A out_msg.DataBlk := getDirectoryEntry(address).DataBlk; 6849831SN/A out_msg.MessageSize := MessageSizeType:Response_Data; 6859831SN/A out_msg.Dirty := in_msg.Dirty; 6869831SN/A out_msg.State := CoherenceState:Modified; 6879831SN/A out_msg.CtoD := false; 6889831SN/A out_msg.InitialRequestTime := in_msg.InitialRequestTime; 6899831SN/A out_msg.ForwardRequestTime := curCycle(); 6909967SN/A out_msg.ProbeRequestStartTime := in_msg.ProbeRequestStartTime; 69110618SOmar.Naji@arm.com out_msg.OriginalResponder := tbe.LastSender; 6929243SN/A out_msg.DemandRequest := false; 6939967SN/A out_msg.L3Hit := tbe.L3Hit; 69410245Sandreas.hansson@arm.com out_msg.WTRequestor := in_msg.WTRequestor; 69510618SOmar.Naji@arm.com DPRINTF(RubySlicc, "%s\n", out_msg); 6969243SN/A } 6979967SN/A } 6989967SN/A enqueue(triggerQueue_out, TriggerMsg, 1) { 69910618SOmar.Naji@arm.com out_msg.addr := address; 7009243SN/A out_msg.Type := TriggerType:UnblockWriteThrough; 7019243SN/A } 7029243SN/A } 7039243SN/A } 7049243SN/A 7059243SN/A action(mb_sendResponseMBypass, "mb", desc="send Modified response") { 70610206Sandreas.hansson@arm.com peek(requestNetwork_in, CPURequestMsg) { 70710206Sandreas.hansson@arm.com enqueue(responseNetwork_out, ResponseMsg, response_latency) { 7089243SN/A out_msg.addr := address; 7099243SN/A out_msg.Type := CoherenceResponseType:NBSysResp; 71010208Sandreas.hansson@arm.com if (tbe.L3Hit) { 71112084Sspwilson2@wisc.edu out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0)); 71210208Sandreas.hansson@arm.com } else { 7139243SN/A out_msg.Sender := machineID; 71412084Sspwilson2@wisc.edu } 7159243SN/A out_msg.Destination.add(in_msg.Requestor); 7169243SN/A out_msg.DataBlk := tbe.DataBlk; 7179243SN/A out_msg.MessageSize := MessageSizeType:Response_Data; 7189243SN/A out_msg.Dirty := tbe.Dirty; 7199831SN/A out_msg.State := CoherenceState:Modified; 7209243SN/A out_msg.CtoD := false; 7219243SN/A out_msg.InitialRequestTime := in_msg.InitialRequestTime; 7229831SN/A out_msg.ForwardRequestTime := curCycle(); 7239243SN/A out_msg.ProbeRequestStartTime := in_msg.ProbeRequestStartTime; 7249243SN/A out_msg.OriginalResponder := tbe.LastSender; 7259243SN/A out_msg.DemandRequest := false; 7269243SN/A out_msg.L3Hit := tbe.L3Hit; 7279831SN/A DPRINTF(RubySlicc, "%s\n", out_msg); 7289243SN/A } 7299243SN/A } 7309831SN/A } 7319243SN/A 7329243SN/A action(c_sendResponseCtoD, "c", desc="send CtoD Ack") { 7339243SN/A enqueue(responseNetwork_out, ResponseMsg, response_latency) { 7349243SN/A out_msg.addr := address; 7359831SN/A out_msg.Type := CoherenceResponseType:NBSysResp; 7369831SN/A out_msg.Sender := machineID; 7379831SN/A out_msg.Destination.add(tbe.OriginalRequestor); 7389243SN/A out_msg.MessageSize := MessageSizeType:Response_Control; 7399243SN/A out_msg.Dirty := false; 7409243SN/A out_msg.State := CoherenceState:Modified; 7419243SN/A out_msg.CtoD := true; 7429831SN/A out_msg.InitialRequestTime := tbe.InitialRequestTime; 7439831SN/A out_msg.ForwardRequestTime := curCycle(); 7449831SN/A out_msg.ProbeRequestStartTime := tbe.ProbeRequestStartTime; 7459243SN/A out_msg.DemandRequest := tbe.DemandRequest; 7469831SN/A DPRINTF(RubySlicc, "%s\n", out_msg); 7479243SN/A } 7489243SN/A } 7499243SN/A 7509243SN/A action(cp_sendResponseCtoDP, "cp", desc="send CtoD Ack") { 7519243SN/A peek(requestNetwork_in, CPURequestMsg) { 7529243SN/A enqueue(responseNetwork_out, ResponseMsg, response_latency) { 7539243SN/A out_msg.addr := address; 7549243SN/A out_msg.Type := CoherenceResponseType:NBSysResp; 7559831SN/A out_msg.Sender := machineID; 7569831SN/A out_msg.Destination.add(in_msg.Requestor); 7579831SN/A out_msg.MessageSize := MessageSizeType:Response_Control; 7589243SN/A out_msg.Dirty := false; 7599831SN/A out_msg.State := CoherenceState:Modified; 7609243SN/A out_msg.CtoD := true; 7619243SN/A out_msg.InitialRequestTime := in_msg.InitialRequestTime; 7629243SN/A out_msg.ForwardRequestTime := curCycle(); 7639243SN/A out_msg.ProbeRequestStartTime := in_msg.ProbeRequestStartTime; 7649243SN/A out_msg.DemandRequest := false; 7659243SN/A DPRINTF(RubySlicc, "%s\n", out_msg); 7669243SN/A } 7679243SN/A } 7689243SN/A } 7699243SN/A 7709243SN/A action(w_sendResponseWBAck, "w", desc="send WB Ack") { 7719243SN/A peek(regDir_in, CPURequestMsg) { 7729243SN/A enqueue(responseNetwork_out, ResponseMsg, response_latency) { 7739243SN/A out_msg.addr := address; 7749243SN/A out_msg.Type := CoherenceResponseType:NBSysWBAck; 7759243SN/A out_msg.Destination.add(in_msg.Requestor); 7769243SN/A out_msg.WTRequestor := in_msg.WTRequestor; 7779243SN/A out_msg.Sender := machineID; 7789243SN/A out_msg.MessageSize := MessageSizeType:Writeback_Control; 7799243SN/A out_msg.InitialRequestTime := in_msg.InitialRequestTime; 7809726SN/A out_msg.ForwardRequestTime := in_msg.ForwardRequestTime; 7819243SN/A out_msg.ProbeRequestStartTime := in_msg.ProbeRequestStartTime; 7829726SN/A out_msg.DemandRequest := false; 7839243SN/A } 7849243SN/A } 7859243SN/A } 7869831SN/A 7879831SN/A action(wp_sendResponseWBAckP, "wp", desc="send WB Ack") { 7889831SN/A peek(requestNetwork_in, CPURequestMsg) { 7899243SN/A enqueue(responseNetwork_out, ResponseMsg, response_latency) { 7909243SN/A out_msg.addr := address; 7919831SN/A out_msg.Type := CoherenceResponseType:NBSysWBAck; 7929831SN/A out_msg.Destination.add(in_msg.Requestor); 7939966SN/A out_msg.WTRequestor := in_msg.WTRequestor; 7949243SN/A out_msg.Sender := machineID; 7959243SN/A out_msg.MessageSize := MessageSizeType:Writeback_Control; 79610143SN/A out_msg.InitialRequestTime := in_msg.InitialRequestTime; 79710143SN/A out_msg.ForwardRequestTime := curCycle(); 7989243SN/A out_msg.ProbeRequestStartTime := in_msg.ProbeRequestStartTime; 7999243SN/A out_msg.DemandRequest := false; 80010206Sandreas.hansson@arm.com } 8019567SN/A } 80210206Sandreas.hansson@arm.com } 80310393Swendy.elsasser@arm.com 80410393Swendy.elsasser@arm.com action(wc_sendResponseWBAck, "wc", desc="send WB Ack for cancel") { 80510393Swendy.elsasser@arm.com peek(responseNetwork_in, ResponseMsg) { 80610393Swendy.elsasser@arm.com enqueue(responseNetwork_out, ResponseMsg, response_latency) { 80710890Swendy.elsasser@arm.com out_msg.addr := address; 80810618SOmar.Naji@arm.com out_msg.Type := CoherenceResponseType:NBSysWBAck; 80910618SOmar.Naji@arm.com out_msg.Destination.add(in_msg.Sender); 8109243SN/A out_msg.Sender := machineID; 81110890Swendy.elsasser@arm.com out_msg.MessageSize := MessageSizeType:Writeback_Control; 8129243SN/A } 8139243SN/A } 8149974SN/A } 81510890Swendy.elsasser@arm.com 81610393Swendy.elsasser@arm.com action(ra_ackRegionDir, "ra", desc="Ack region dir") { 81710393Swendy.elsasser@arm.com peek(regDir_in, CPURequestMsg) { 81810890Swendy.elsasser@arm.com if (in_msg.NoAckNeeded == false) { 81910618SOmar.Naji@arm.com enqueue(responseNetwork_out, ResponseMsg, response_latency_regionDir) { 82010618SOmar.Naji@arm.com out_msg.addr := address; 8219974SN/A out_msg.Type := CoherenceResponseType:DirReadyAck; 82210890Swendy.elsasser@arm.com out_msg.Destination.add(mapAddressToMachine(address, MachineType:RegionDir)); 8239974SN/A out_msg.Sender := machineID; 8249974SN/A out_msg.MessageSize := MessageSizeType:Writeback_Control; 82510211Sandreas.hansson@arm.com } 82610211Sandreas.hansson@arm.com } 82710393Swendy.elsasser@arm.com } 8289967SN/A } 82910393Swendy.elsasser@arm.com 83010890Swendy.elsasser@arm.com action(l_queueMemRdReq, "lr", desc="Read data from memory") { 8319967SN/A peek(regDir_in, CPURequestMsg) { 83210890Swendy.elsasser@arm.com if (L3CacheMemory.isTagPresent(address)) { 8339967SN/A enqueue(L3TriggerQueue_out, TriggerMsg, l3_hit_latency) { 83410890Swendy.elsasser@arm.com out_msg.addr := address; 83510890Swendy.elsasser@arm.com out_msg.Type := TriggerType:L3Hit; 8369488SN/A DPRINTF(RubySlicc, "%s\n", out_msg); 8379488SN/A } 8389488SN/A CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(address)); 8399488SN/A tbe.DataBlk := entry.DataBlk; 8409488SN/A tbe.LastSender := entry.LastSender; 8419488SN/A tbe.L3Hit := true; 84210210Sandreas.hansson@arm.com tbe.MemData := true; 84310618SOmar.Naji@arm.com DPRINTF(RubySlicc, "L3 data is %s\n", entry.DataBlk); 84410618SOmar.Naji@arm.com L3CacheMemory.deallocate(address); 84510210Sandreas.hansson@arm.com } else { 84610210Sandreas.hansson@arm.com queueMemoryRead(machineID, address, to_memory_controller_latency); 8479488SN/A } 84810618SOmar.Naji@arm.com } 84910618SOmar.Naji@arm.com } 85010207Sandreas.hansson@arm.com 85110207Sandreas.hansson@arm.com action(lrp_queueMemRdReqP, "lrp", desc="Read data from memory") { 85210207Sandreas.hansson@arm.com peek(requestNetwork_in, CPURequestMsg) { 85310207Sandreas.hansson@arm.com if (L3CacheMemory.isTagPresent(address)) { 85410207Sandreas.hansson@arm.com enqueue(L3TriggerQueue_out, TriggerMsg, l3_hit_latency) { 85510207Sandreas.hansson@arm.com out_msg.addr := address; 85610618SOmar.Naji@arm.com out_msg.Type := TriggerType:L3Hit; 85710247Sandreas.hansson@arm.com DPRINTF(RubySlicc, "%s\n", out_msg); 85810211Sandreas.hansson@arm.com } 85910247Sandreas.hansson@arm.com CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(address)); 86010207Sandreas.hansson@arm.com tbe.DataBlk := entry.DataBlk; 86110618SOmar.Naji@arm.com tbe.LastSender := entry.LastSender; 86210618SOmar.Naji@arm.com tbe.L3Hit := true; 8639488SN/A tbe.MemData := true; 86410143SN/A DPRINTF(RubySlicc, "L3 data is %s\n", entry.DataBlk); 86510143SN/A L3CacheMemory.deallocate(address); 86610143SN/A } else { 8679243SN/A queueMemoryRead(machineID, address, to_memory_controller_latency); 8689243SN/A } 8699243SN/A } 87010889Sandreas.hansson@arm.com } 87110889Sandreas.hansson@arm.com 87210889Sandreas.hansson@arm.com action(dcr_probeInvCoreData, "dcr", desc="probe inv cores, return data") { 87310889Sandreas.hansson@arm.com peek(regBuf_in, CPURequestMsg) { 87410889Sandreas.hansson@arm.com enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) { 87510889Sandreas.hansson@arm.com out_msg.addr := address; 87610889Sandreas.hansson@arm.com out_msg.Type := ProbeRequestType:PrbInv; 87710889Sandreas.hansson@arm.com out_msg.ReturnData := true; 87810889Sandreas.hansson@arm.com out_msg.MessageSize := MessageSizeType:Control; 8799243SN/A out_msg.Destination := in_msg.Sharers; 8809243SN/A tbe.NumPendingAcks := tbe.NumPendingAcks + in_msg.Sharers.count(); 8819833SN/A DPRINTF(RubySlicc, "%s\n", out_msg); 8829833SN/A APPEND_TRANSITION_COMMENT(" dcr: Acks remaining: "); 8839243SN/A APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks); 8849243SN/A tbe.ProbeRequestStartTime := curCycle(); 88510889Sandreas.hansson@arm.com } 88610889Sandreas.hansson@arm.com } 88710889Sandreas.hansson@arm.com } 88810889Sandreas.hansson@arm.com 88910889Sandreas.hansson@arm.com action(ddr_probeDownCoreData, "ddr", desc="probe inv cores, return data") { 89010889Sandreas.hansson@arm.com peek(regBuf_in, CPURequestMsg) { 89110889Sandreas.hansson@arm.com enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) { 89210889Sandreas.hansson@arm.com out_msg.addr := address; 89310889Sandreas.hansson@arm.com out_msg.Type := ProbeRequestType:PrbDowngrade; 8949243SN/A out_msg.ReturnData := true; 8959567SN/A out_msg.MessageSize := MessageSizeType:Control; 8969567SN/A out_msg.Destination := in_msg.Sharers; 8979567SN/A tbe.NumPendingAcks := tbe.NumPendingAcks + in_msg.Sharers.count(); 8989567SN/A DPRINTF(RubySlicc, "%s\n", out_msg); 8999567SN/A APPEND_TRANSITION_COMMENT(" dcr: Acks remaining: "); 9009243SN/A APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks); 9019833SN/A tbe.ProbeRequestStartTime := curCycle(); 9029243SN/A } 9039567SN/A } 90410618SOmar.Naji@arm.com } 9059243SN/A 90610618SOmar.Naji@arm.com action(sc_probeShrCoreData, "sc", desc="probe shared cores, return data") { 9079243SN/A peek(requestNetwork_in, CPURequestMsg) { // not the right network? 9089243SN/A enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) { 9099243SN/A out_msg.addr := address; 9109831SN/A out_msg.Type := ProbeRequestType:PrbDowngrade; 9119831SN/A out_msg.ReturnData := true; 9129831SN/A out_msg.MessageSize := MessageSizeType:Control; 9139243SN/A out_msg.Destination.broadcast(MachineType:CorePair); // won't be realistic for multisocket 91410489SOmar.Naji@arm.com tbe.NumPendingAcks := tbe.NumPendingAcks +machineCount(MachineType:CorePair) - 1; 9159831SN/A out_msg.Destination.broadcast(MachineType:TCP); 9169831SN/A tbe.NumPendingAcks := tbe.NumPendingAcks + machineCount(MachineType:TCP); 9179831SN/A out_msg.Destination.broadcast(MachineType:SQC); 9189831SN/A tbe.NumPendingAcks := tbe.NumPendingAcks + machineCount(MachineType:SQC); 9199831SN/A out_msg.Destination.remove(in_msg.Requestor); 9209831SN/A DPRINTF(RubySlicc, "%s\n", (out_msg)); 92110140SN/A APPEND_TRANSITION_COMMENT(" sc: Acks remaining: "); 92210286Sandreas.hansson@arm.com APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks); 9239243SN/A tbe.ProbeRequestStartTime := curCycle(); 92410394Swendy.elsasser@arm.com } 92510394Swendy.elsasser@arm.com } 9269243SN/A } 9279566SN/A 9289243SN/A action(ic_probeInvCore, "ic", desc="probe invalidate core, no return data needed") { 9299243SN/A peek(requestNetwork_in, CPURequestMsg) { // not the right network? 9309243SN/A enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) { 93110140SN/A out_msg.addr := address; 93210140SN/A out_msg.Type := ProbeRequestType:PrbInv; 93310140SN/A out_msg.ReturnData := false; 93410140SN/A out_msg.MessageSize := MessageSizeType:Control; 93510147Sandreas.hansson@arm.com out_msg.Destination.broadcast(MachineType:CorePair); // won't be realistic for multisocket 9369243SN/A tbe.NumPendingAcks := tbe.NumPendingAcks +machineCount(MachineType:CorePair) - 1; 9379243SN/A out_msg.Destination.broadcast(MachineType:TCP); 9389243SN/A tbe.NumPendingAcks := tbe.NumPendingAcks + machineCount(MachineType:TCP); 9399243SN/A out_msg.Destination.broadcast(MachineType:SQC); 9409243SN/A tbe.NumPendingAcks := tbe.NumPendingAcks + machineCount(MachineType:SQC); 94110286Sandreas.hansson@arm.com out_msg.Destination.remove(in_msg.Requestor); 9429243SN/A APPEND_TRANSITION_COMMENT(" ic: Acks remaining: "); 94310206Sandreas.hansson@arm.com APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks); 94410393Swendy.elsasser@arm.com DPRINTF(RubySlicc, "%s\n", out_msg); 9459243SN/A tbe.ProbeRequestStartTime := curCycle(); 94610394Swendy.elsasser@arm.com } 9479243SN/A } 9489243SN/A } 9499243SN/A 9509963SN/A action(d_writeDataToMemory, "d", desc="Write data to memory") { 95110210Sandreas.hansson@arm.com peek(responseNetwork_in, ResponseMsg) { 95210212Sandreas.hansson@arm.com getDirectoryEntry(address).DataBlk := in_msg.DataBlk; 9539243SN/A DPRINTF(RubySlicc, "Writing Data: %s to address %s\n", in_msg.DataBlk, 9549243SN/A in_msg.addr); 9559971SN/A } 95610394Swendy.elsasser@arm.com } 9579488SN/A 95811673SOmar.Naji@arm.com action(t_allocateTBE, "t", desc="allocate TBE Entry") { 95911673SOmar.Naji@arm.com check_allocate(TBEs); 9609488SN/A peek(regDir_in, CPURequestMsg) { 9619243SN/A TBEs.allocate(address); 9629243SN/A set_tbe(TBEs.lookup(address)); 9639243SN/A if (in_msg.Type == CoherenceRequestType:WriteThrough) { 9649243SN/A tbe.writeMask.clear(); 9659243SN/A tbe.writeMask.orMask(in_msg.writeMask); 9669243SN/A tbe.wtData := true; 9679243SN/A tbe.WTRequestor := in_msg.WTRequestor; 9689243SN/A tbe.LastSender := in_msg.Requestor; 9699243SN/A } 9709243SN/A if (in_msg.Type == CoherenceRequestType:Atomic) { 97110141SN/A tbe.writeMask.clear(); 97210141SN/A tbe.writeMask.orMask(in_msg.writeMask); 97310141SN/A tbe.atomicData := true; 97410141SN/A tbe.WTRequestor := in_msg.WTRequestor; 97510141SN/A tbe.LastSender := in_msg.Requestor; 97610141SN/A } 9779726SN/A tbe.DataBlk := getDirectoryEntry(address).DataBlk; // Data only for WBs 9789726SN/A tbe.Dirty := false; 9799726SN/A if (in_msg.Type == CoherenceRequestType:WriteThrough) { 9809726SN/A tbe.DataBlk.copyPartial(in_msg.DataBlk,tbe.writeMask); 9819726SN/A tbe.Dirty := false; 9829726SN/A } 9839726SN/A tbe.OriginalRequestor := in_msg.Requestor; 9849726SN/A tbe.NumPendingAcks := 0; 9859726SN/A tbe.Cached := in_msg.ForceShared; 9869726SN/A tbe.InitialRequestTime := in_msg.InitialRequestTime; 9879726SN/A tbe.ForwardRequestTime := curCycle(); 9889726SN/A tbe.ProbeRequestStartTime := in_msg.ProbeRequestStartTime; 9899726SN/A tbe.DemandRequest := in_msg.DemandRequest; 9909726SN/A } 9919243SN/A } 9929243SN/A 9939243SN/A action(tp_allocateTBEP, "tp", desc="allocate TBE Entry") { 9949243SN/A check_allocate(TBEs); 9959243SN/A peek(requestNetwork_in, CPURequestMsg) { 9969243SN/A TBEs.allocate(address); 99710206Sandreas.hansson@arm.com set_tbe(TBEs.lookup(address)); 99810206Sandreas.hansson@arm.com if (in_msg.Type == CoherenceRequestType:WriteThrough) { 99910206Sandreas.hansson@arm.com tbe.writeMask.clear(); 100010206Sandreas.hansson@arm.com tbe.writeMask.orMask(in_msg.writeMask); 100110206Sandreas.hansson@arm.com tbe.wtData := true; 100210206Sandreas.hansson@arm.com tbe.WTRequestor := in_msg.WTRequestor; 100310206Sandreas.hansson@arm.com tbe.LastSender := in_msg.Requestor; 10049972SN/A } 10059243SN/A if (in_msg.Type == CoherenceRequestType:Atomic) { 10069243SN/A tbe.writeMask.clear(); 10079243SN/A tbe.writeMask.orMask(in_msg.writeMask); 10089831SN/A tbe.atomicData := true; 10099831SN/A tbe.WTRequestor := in_msg.WTRequestor; 10109975SN/A tbe.LastSender := in_msg.Requestor; 10119975SN/A } 10129243SN/A tbe.DataBlk := getDirectoryEntry(address).DataBlk; // Data only for WBs 10139977SN/A tbe.Dirty := false; 10149977SN/A if (in_msg.Type == CoherenceRequestType:WriteThrough) { 10159243SN/A tbe.DataBlk.copyPartial(in_msg.DataBlk,tbe.writeMask); 10169977SN/A tbe.Dirty := false; 10179243SN/A } 10189977SN/A tbe.OriginalRequestor := in_msg.Requestor; 10199977SN/A tbe.NumPendingAcks := 0; 10209243SN/A tbe.Cached := in_msg.ForceShared; 10219243SN/A tbe.InitialRequestTime := in_msg.InitialRequestTime; 10229243SN/A tbe.ForwardRequestTime := curCycle(); 10239243SN/A tbe.ProbeRequestStartTime := in_msg.ProbeRequestStartTime; 10249243SN/A tbe.DemandRequest := false; 10259243SN/A } 10269243SN/A } 10279727SN/A 102810147Sandreas.hansson@arm.com action(sa_setAcks, "sa", desc="setAcks") { 102910147Sandreas.hansson@arm.com peek(regDir_in, CPURequestMsg) { 10309243SN/A tbe.NumPendingAcks := in_msg.Acks; 10319243SN/A APPEND_TRANSITION_COMMENT(" waiting for acks "); 10329243SN/A APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks); 10339243SN/A } 10349243SN/A } 10359243SN/A 10369243SN/A action(tr_allocateTBE, "tr", desc="allocate TBE Entry for Region inv") { 10379243SN/A check_allocate(TBEs); 10389243SN/A TBEs.allocate(address); 10399243SN/A set_tbe(TBEs.lookup(address)); 10409243SN/A tbe.NumPendingAcks := 0; 10419243SN/A } 10429243SN/A 10439243SN/A action(dt_deallocateTBE, "dt", desc="deallocate TBE Entry") { 10449977SN/A TBEs.deallocate(address); 10459977SN/A unset_tbe(); 10469243SN/A } 10479243SN/A 10489975SN/A action(wdp_writeBackDataPrivate, "wdp", desc="Write back data if needed") { 10499975SN/A peek(requestNetwork_in, CPURequestMsg) { 10509243SN/A if (in_msg.Type == CoherenceRequestType:WriteThrough) { 10519243SN/A tbe.DataBlkAux := getDirectoryEntry(address).DataBlk; 10529243SN/A tbe.DataBlkAux.copyPartial(in_msg.DataBlk,in_msg.writeMask); 10539243SN/A getDirectoryEntry(address).DataBlk := tbe.DataBlkAux; 10549243SN/A } else{ 10559243SN/A assert(in_msg.Type == CoherenceRequestType:Atomic); 10569243SN/A tbe.DataBlkAux.atomicPartial(getDirectoryEntry(address).DataBlk,in_msg.writeMask); 10579243SN/A getDirectoryEntry(address).DataBlk := tbe.DataBlkAux; 10589243SN/A } 10599243SN/A } 10609243SN/A } 10619243SN/A 10629975SN/A action(wd_writeBackData, "wd", desc="Write back data if needed") { 10639975SN/A if (tbe.wtData) { 10649975SN/A DataBlock tmp := getDirectoryEntry(address).DataBlk; 106510393Swendy.elsasser@arm.com tmp.copyPartial(tbe.DataBlk,tbe.writeMask); 106610393Swendy.elsasser@arm.com tbe.DataBlk := tmp; 106710393Swendy.elsasser@arm.com getDirectoryEntry(address).DataBlk := tbe.DataBlk; 106810432SOmar.Naji@arm.com } else if (tbe.atomicData) { 106910432SOmar.Naji@arm.com tbe.DataBlk.atomicPartial(getDirectoryEntry(address).DataBlk,tbe.writeMask); 107010432SOmar.Naji@arm.com getDirectoryEntry(address).DataBlk := tbe.DataBlk; 107112266Sradhika.jagtap@arm.com } else if (tbe.Dirty == true) { 107212266Sradhika.jagtap@arm.com APPEND_TRANSITION_COMMENT(" Wrote data back "); 107312266Sradhika.jagtap@arm.com getDirectoryEntry(address).DataBlk := tbe.DataBlk; 107411190Sandreas.hansson@arm.com } 107511190Sandreas.hansson@arm.com } 107611190Sandreas.hansson@arm.com 10779349SN/A action(wdi_writeBackDataInv, "wdi", desc="Write back inv data if needed") { 107811190Sandreas.hansson@arm.com // Kind of opposite from above...? 10799349SN/A if (tbe.Dirty == true) { 108010432SOmar.Naji@arm.com getDirectoryEntry(address).DataBlk := tbe.DataBlk; 108110618SOmar.Naji@arm.com APPEND_TRANSITION_COMMENT("Writing dirty data to dir"); 108210618SOmar.Naji@arm.com DPRINTF(RubySlicc, "Data %s: %s\n", address, tbe.DataBlk); 108310618SOmar.Naji@arm.com } else { 108410618SOmar.Naji@arm.com APPEND_TRANSITION_COMMENT("NOT!!! Writing dirty data to dir"); 108510618SOmar.Naji@arm.com } 108610618SOmar.Naji@arm.com } 108710618SOmar.Naji@arm.com 108810618SOmar.Naji@arm.com action(wdt_writeBackDataInvNoTBE, "wdt", desc="Write back inv data if needed no TBE") { 108910618SOmar.Naji@arm.com // Kind of opposite from above...? 109010432SOmar.Naji@arm.com peek(responseNetwork_in, ResponseMsg) { 109110432SOmar.Naji@arm.com if (in_msg.Dirty == true) { 109211675Swendy.elsasser@arm.com getDirectoryEntry(address).DataBlk := in_msg.DataBlk; 109310432SOmar.Naji@arm.com APPEND_TRANSITION_COMMENT("Writing dirty data to dir"); 109411675Swendy.elsasser@arm.com DPRINTF(RubySlicc, "Data %s: %s\n", address, in_msg.DataBlk); 109511675Swendy.elsasser@arm.com } else { 109611675Swendy.elsasser@arm.com APPEND_TRANSITION_COMMENT("NOT!!! Writing dirty data to dir"); 109710432SOmar.Naji@arm.com } 109811675Swendy.elsasser@arm.com } 109911675Swendy.elsasser@arm.com } 110010432SOmar.Naji@arm.com 110110432SOmar.Naji@arm.com action(mt_writeMemDataToTBE, "mt", desc="write Mem data to TBE") { 11029243SN/A peek(memQueue_in, MemoryMsg) { 11039243SN/A if (tbe.Dirty == false) { 110411169Sandreas.hansson@arm.com tbe.DataBlk := getDirectoryEntry(address).DataBlk; 11059243SN/A } 110610146Sandreas.hansson@arm.com tbe.MemData := true; 11079243SN/A } 110811168Sandreas.hansson@arm.com } 11099243SN/A 11109294SN/A action(ml_writeL3DataToTBE, "ml", desc="write L3 data to TBE") { 111111169Sandreas.hansson@arm.com assert(tbe.Dirty == false); 11129243SN/A CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(address)); 111311168Sandreas.hansson@arm.com tbe.DataBlk := entry.DataBlk; 111411168Sandreas.hansson@arm.com tbe.LastSender := entry.LastSender; 111511168Sandreas.hansson@arm.com tbe.L3Hit := true; 11169243SN/A tbe.MemData := true; 111711676Swendy.elsasser@arm.com } 111811676Swendy.elsasser@arm.com 111911676Swendy.elsasser@arm.com action(y_writeProbeDataToTBE, "y", desc="write Probe Data to TBE") { 112011676Swendy.elsasser@arm.com peek(responseNetwork_in, ResponseMsg) { 112111676Swendy.elsasser@arm.com if (in_msg.Dirty) { 112211676Swendy.elsasser@arm.com DPRINTF(RubySlicc, "Got dirty data for %s from %s\n", address, in_msg.Sender); 112311676Swendy.elsasser@arm.com DPRINTF(RubySlicc, "Data is %s\n", in_msg.DataBlk); 112411676Swendy.elsasser@arm.com if (tbe.wtData) { 112511676Swendy.elsasser@arm.com DataBlock tmp := in_msg.DataBlk; 112611676Swendy.elsasser@arm.com tmp.copyPartial(tbe.DataBlk,tbe.writeMask); 112711676Swendy.elsasser@arm.com tbe.DataBlk := tmp; 11289243SN/A } else if (tbe.Dirty) { 11299243SN/A if(tbe.atomicData == false && tbe.wtData == false) { 11309243SN/A DPRINTF(RubySlicc, "Got double data for %s from %s\n", address, in_msg.Sender); 11319243SN/A assert(tbe.DataBlk == in_msg.DataBlk); // in case of double data 11329243SN/A } 11339243SN/A } else { 11349243SN/A tbe.DataBlk := in_msg.DataBlk; 11359243SN/A tbe.Dirty := in_msg.Dirty; 113610146Sandreas.hansson@arm.com tbe.LastSender := in_msg.Sender; 1137 } 1138 } 1139 if (in_msg.Hit) { 1140 tbe.Cached := true; 1141 } 1142 } 1143 } 1144 1145 action(yc_writeCPUDataToTBE, "yc", desc="write CPU Data to TBE") { 1146 peek(responseNetwork_in, ResponseMsg) { 1147 if (in_msg.Dirty) { 1148 DPRINTF(RubySlicc, "Got dirty data for %s from %s\n", address, in_msg.Sender); 1149 DPRINTF(RubySlicc, "Data is %s\n", in_msg.DataBlk); 1150 if (tbe.Dirty) { 1151 DPRINTF(RubySlicc, "Got double data for %s from %s\n", address, in_msg.Sender); 1152 assert(tbe.DataBlk == in_msg.DataBlk); // in case of double data 1153 } 1154 tbe.DataBlk := in_msg.DataBlk; 1155 tbe.Dirty := false; 1156 tbe.LastSender := in_msg.Sender; 1157 } 1158 } 1159 } 1160 1161 action(x_decrementAcks, "x", desc="decrement Acks pending") { 1162 if (tbe.NumPendingAcks > 0) { 1163 tbe.NumPendingAcks := tbe.NumPendingAcks - 1; 1164 } else { 1165 APPEND_TRANSITION_COMMENT(" Double ack! "); 1166 } 1167 assert(tbe.NumPendingAcks >= 0); 1168 APPEND_TRANSITION_COMMENT(" Acks remaining: "); 1169 APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks); 1170 } 1171 1172 action(o_checkForCompletion, "o", desc="check for ack completion") { 1173 if (tbe.NumPendingAcks == 0 && tbe.TriggeredAcksComplete == false) { 1174 enqueue(triggerQueue_out, TriggerMsg, 1) { 1175 out_msg.addr := address; 1176 out_msg.Type := TriggerType:AcksComplete; 1177 } 1178 tbe.TriggeredAcksComplete := true; 1179 } 1180 APPEND_TRANSITION_COMMENT(" Check: Acks remaining: "); 1181 APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks); 1182 } 1183 1184 action(ont_checkForCompletionNoTrigger, "ont", desc="check for ack completion, no trigger") { 1185 if (tbe.NumPendingAcks == 0 && tbe.TriggeredAcksComplete == false) { 1186 tbe.TriggeredAcksComplete := true; 1187 } 1188 APPEND_TRANSITION_COMMENT(" Check: Acks remaining: "); 1189 APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks); 1190 } 1191 1192 action(rvp_removeVicDirtyIgnore, "rvp", desc="Remove ignored core") { 1193 peek(requestNetwork_in, CPURequestMsg) { 1194 getDirectoryEntry(address).VicDirtyIgnore.remove(in_msg.Requestor); 1195 } 1196 } 1197 1198 action(rv_removeVicDirtyIgnore, "rv", desc="Remove ignored core") { 1199 peek(regDir_in, CPURequestMsg) { 1200 getDirectoryEntry(address).VicDirtyIgnore.remove(in_msg.Requestor); 1201 } 1202 } 1203 1204 action(r_sendRequestToRegionDir, "r", desc="send request to Region Directory") { 1205 peek(requestNetwork_in, CPURequestMsg) { 1206 enqueue(requestNetworkReg_out, CPURequestMsg, 1) { 1207 out_msg.addr := address; 1208 out_msg.Type := in_msg.Type; 1209 out_msg.Requestor := in_msg.Requestor; 1210 out_msg.Destination.add(mapAddressToMachine(address, MachineType:RegionDir)); 1211 out_msg.Shared := in_msg.Shared; 1212 out_msg.MessageSize := in_msg.MessageSize; 1213 DPRINTF(RubySlicc, "out dest: %s\n", mapAddressToMachine(address, MachineType:RegionDir)); 1214 } 1215 } 1216 } 1217 1218 action(ai_ackInvalidate, "ai", desc="Ack to let the reg-dir know that the inv is ordered") { 1219 peek(regBuf_in, CPURequestMsg) { 1220 enqueue(regAckNetwork_out, UnblockMsg, 1) { 1221 out_msg.addr := address; 1222 out_msg.Destination.add(in_msg.Requestor); 1223 out_msg.MessageSize := MessageSizeType:Response_Control; 1224 DPRINTF(RubySlicc, "ai out_msg: %s\n", out_msg); 1225 } 1226 } 1227 } 1228 1229 action(aic_ackInvalidate, "aic", desc="Ack to let the reg-dir know that the inv is ordered") { 1230 peek(responseNetwork_in, ResponseMsg) { 1231 if (in_msg.NoAckNeeded == false) { 1232 enqueue(regAckNetwork_out, UnblockMsg, 1) { 1233 out_msg.addr := address; 1234 if (machineIDToMachineType(in_msg.Sender) == MachineType:CorePair) { 1235 out_msg.Destination.add(createMachineID(MachineType:RegionBuffer, intToID(0))); 1236 } else { 1237 out_msg.Destination.add(createMachineID(MachineType:RegionBuffer, intToID(1))); 1238 } 1239 out_msg.MessageSize := MessageSizeType:Response_Control; 1240 DPRINTF(RubySlicc, "ai out_msg: %s\n", out_msg); 1241 out_msg.wasValid := in_msg.isValid; 1242 } 1243 } 1244 } 1245 } 1246 1247 action(al_allocateL3Block, "al", desc="allocate the L3 block on WB") { 1248 peek(responseNetwork_in, ResponseMsg) { 1249 if (L3CacheMemory.isTagPresent(address)) { 1250 CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(address)); 1251 APPEND_TRANSITION_COMMENT(" al wrote data to L3 (hit) "); 1252 entry.DataBlk := in_msg.DataBlk; 1253 entry.LastSender := in_msg.Sender; 1254 } else { 1255 if (L3CacheMemory.cacheAvail(address) == false) { 1256 Addr victim := L3CacheMemory.cacheProbe(address); 1257 CacheEntry victim_entry := static_cast(CacheEntry, "pointer", 1258 L3CacheMemory.lookup(victim)); 1259 queueMemoryWrite(machineID, victim, to_memory_controller_latency, 1260 victim_entry.DataBlk); 1261 L3CacheMemory.deallocate(victim); 1262 } 1263 assert(L3CacheMemory.cacheAvail(address)); 1264 CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry)); 1265 APPEND_TRANSITION_COMMENT(" al wrote data to L3 "); 1266 entry.DataBlk := in_msg.DataBlk; 1267 entry.LastSender := in_msg.Sender; 1268 } 1269 } 1270 } 1271 1272 action(alwt_allocateL3BlockOnWT, "alwt", desc="allocate the L3 block on WT") { 1273 if ((tbe.wtData || tbe.atomicData) && useL3OnWT) { 1274 if (L3CacheMemory.isTagPresent(address)) { 1275 CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(address)); 1276 APPEND_TRANSITION_COMMENT(" al wrote data to L3 (hit) "); 1277 entry.DataBlk := tbe.DataBlk; 1278 entry.LastSender := tbe.LastSender; 1279 } else { 1280 if (L3CacheMemory.cacheAvail(address) == false) { 1281 Addr victim := L3CacheMemory.cacheProbe(address); 1282 CacheEntry victim_entry := static_cast(CacheEntry, "pointer", 1283 L3CacheMemory.lookup(victim)); 1284 queueMemoryWrite(machineID, victim, to_memory_controller_latency, 1285 victim_entry.DataBlk); 1286 L3CacheMemory.deallocate(victim); 1287 } 1288 assert(L3CacheMemory.cacheAvail(address)); 1289 CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry)); 1290 APPEND_TRANSITION_COMMENT(" al wrote data to L3 "); 1291 entry.DataBlk := tbe.DataBlk; 1292 entry.LastSender := tbe.LastSender; 1293 } 1294 } 1295 } 1296 1297 action(ali_allocateL3Block, "ali", desc="allocate the L3 block on ForceInv") { 1298 if (tbe.Dirty == true) { 1299 if (L3CacheMemory.isTagPresent(address)) { 1300 CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(address)); 1301 APPEND_TRANSITION_COMMENT(" al wrote data to L3 (hit) "); 1302 entry.DataBlk := tbe.DataBlk; 1303 entry.LastSender := tbe.LastSender; 1304 } else { 1305 if (L3CacheMemory.cacheAvail(address) == false) { 1306 Addr victim := L3CacheMemory.cacheProbe(address); 1307 CacheEntry victim_entry := static_cast(CacheEntry, "pointer", 1308 L3CacheMemory.lookup(victim)); 1309 queueMemoryWrite(machineID, victim, to_memory_controller_latency, 1310 victim_entry.DataBlk); 1311 L3CacheMemory.deallocate(victim); 1312 } 1313 assert(L3CacheMemory.cacheAvail(address)); 1314 CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry)); 1315 APPEND_TRANSITION_COMMENT(" al wrote data to L3 "); 1316 entry.DataBlk := tbe.DataBlk; 1317 entry.LastSender := tbe.LastSender; 1318 } 1319 } 1320 } 1321 1322 action(ali_allocateL3BlockNoTBE, "alt", desc="allocate the L3 block on ForceInv no TBE") { 1323 peek(responseNetwork_in, ResponseMsg) { 1324 if (in_msg.Dirty) { 1325 if (L3CacheMemory.isTagPresent(address)) { 1326 CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(address)); 1327 APPEND_TRANSITION_COMMENT(" ali wrote data to L3 (hit) "); 1328 entry.DataBlk := in_msg.DataBlk; 1329 entry.LastSender := in_msg.Sender; 1330 } else { 1331 if (L3CacheMemory.cacheAvail(address) == false) { 1332 Addr victim := L3CacheMemory.cacheProbe(address); 1333 CacheEntry victim_entry := static_cast(CacheEntry, "pointer", 1334 L3CacheMemory.lookup(victim)); 1335 queueMemoryWrite(machineID, victim, to_memory_controller_latency, 1336 victim_entry.DataBlk); 1337 L3CacheMemory.deallocate(victim); 1338 } 1339 assert(L3CacheMemory.cacheAvail(address)); 1340 CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry)); 1341 APPEND_TRANSITION_COMMENT(" ali wrote data to L3 "); 1342 entry.DataBlk := in_msg.DataBlk; 1343 entry.LastSender := in_msg.Sender; 1344 } 1345 } 1346 } 1347 } 1348 1349 action(dl_deallocateL3, "dl", desc="deallocate the L3 block") { 1350 L3CacheMemory.deallocate(address); 1351 } 1352 1353 action(p_popRequestQueue, "p", desc="pop request queue") { 1354 requestNetwork_in.dequeue(clockEdge()); 1355 } 1356 1357 action(prd_popRegionQueue, "prd", desc="pop request queue") { 1358 regDir_in.dequeue(clockEdge()); 1359 } 1360 1361 action(prb_popRegionBufQueue, "prb", desc="pop request queue") { 1362 regBuf_in.dequeue(clockEdge()); 1363 } 1364 1365 action(pr_popResponseQueue, "pr", desc="pop response queue") { 1366 responseNetwork_in.dequeue(clockEdge()); 1367 } 1368 1369 action(pm_popMemQueue, "pm", desc="pop mem queue") { 1370 memQueue_in.dequeue(clockEdge()); 1371 } 1372 1373 action(pt_popTriggerQueue, "pt", desc="pop trigger queue") { 1374 triggerQueue_in.dequeue(clockEdge()); 1375 } 1376 1377 action(ptl_popTriggerQueue, "ptl", desc="pop L3 trigger queue") { 1378 L3TriggerQueue_in.dequeue(clockEdge()); 1379 } 1380 1381 action(pu_popUnblockQueue, "pu", desc="pop unblock queue") { 1382 unblockNetwork_in.dequeue(clockEdge()); 1383 } 1384 1385 action(yy_recycleResponseQueue, "yy", desc="recycle response queue") { 1386 responseNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); 1387 } 1388 1389 action(ww_stallAndWaitRegRequestQueue, "ww", desc="recycle region dir request queue") { 1390 stall_and_wait(regDir_in, address); 1391 } 1392 1393 action(st_stallAndWaitRequest, "st", desc="Stall and wait on the address") { 1394 stall_and_wait(requestNetwork_in, address); 1395 } 1396 1397 action(wa_wakeUpDependents, "wa", desc="Wake up any requests waiting for this address") { 1398 wakeUpBuffers(address); 1399 } 1400 1401 action(wa_wakeUpAllDependents, "waa", desc="Wake up any requests waiting for this region") { 1402 wakeUpAllBuffers(); 1403 } 1404 1405 action(z_stall, "z", desc="...") { 1406 } 1407 1408 // TRANSITIONS 1409 1410 // transitions from U 1411 1412 transition({BR, BW, BL, BI, BS_M, BM_M, B_M, BP, BS_PM, BM_PM, B_PM, BS_Pm, BM_Pm, B_Pm, B}, {Inv, Downgrade}) { 1413 ww_stallAndWaitRegRequestQueue; 1414 } 1415 1416 transition(U, Inv, BI){L3TagArrayRead} { 1417 tr_allocateTBE; 1418 dcr_probeInvCoreData; // only need to invalidate sharers 1419 ai_ackInvalidate; 1420 prb_popRegionBufQueue; 1421 } 1422 1423 transition(U, Downgrade, BI){L3TagArrayRead} { 1424 tr_allocateTBE; 1425 ddr_probeDownCoreData; // only need to invalidate sharers 1426 ai_ackInvalidate; 1427 prb_popRegionBufQueue; 1428 } 1429 1430 // The next 2 transistions are needed in the event that an invalidation 1431 // is waiting for its ack from the core, but the event makes it through 1432 // the region directory before the acks. This wouldn't be needed if 1433 // we waited to ack the region dir until the directory got all the acks 1434 transition({BR, BW, BI, BL, BS_M, BM_M, B_M, BP, BS_PM, BM_PM, B_PM, BS_Pm, BM_Pm, B_Pm, B}, {RdBlkS, RdBlkM, RdBlk, WriteThrough, Atomic}) { 1435 ww_stallAndWaitRegRequestQueue; 1436 } 1437 1438 transition({BR, BW, BI, BL, BS_M, BM_M, B_M, BS_PM, BM_PM, B_PM, B, BS_Pm_BL, BM_Pm_BL, B_Pm_BL, BP_BL, BS_Pm_B, BM_Pm_B, B_Pm_B, BP_B}, {RdBlkSP, RdBlkMP, RdBlkP}) { 1439 st_stallAndWaitRequest; 1440 } 1441 1442 transition({BR, BW, BI, BL, BS_M, BM_M, B_M, BS_PM, BM_PM, B_PM, B, BS_Pm_BL, BM_Pm_BL, B_Pm_BL, BP_BL, BS_Pm_B, BM_Pm_B, B_Pm_B, BP_B}, {WriteThroughP,AtomicP}) { 1443 st_stallAndWaitRequest; 1444 } 1445 1446 transition(U, {RdBlkS}, BS_PM) {L3TagArrayRead} { 1447 t_allocateTBE; 1448 l_queueMemRdReq; 1449 sa_setAcks; 1450 o_checkForCompletion; 1451 ra_ackRegionDir; 1452 prd_popRegionQueue; 1453 } 1454 1455 transition(U, WriteThrough, BM_PM){L3TagArrayRead} { 1456 t_allocateTBE; 1457 w_sendResponseWBAck; 1458 l_queueMemRdReq; 1459 sa_setAcks; 1460 o_checkForCompletion; 1461 ra_ackRegionDir; 1462 prd_popRegionQueue; 1463 } 1464 1465 transition(U, {RdBlkM,Atomic}, BM_PM){L3TagArrayRead} { 1466 t_allocateTBE; 1467 l_queueMemRdReq; 1468 sa_setAcks; 1469 o_checkForCompletion; 1470 ra_ackRegionDir; 1471 prd_popRegionQueue; 1472 } 1473 1474 transition(U, RdBlk, B_PM){L3TagArrayRead} { 1475 t_allocateTBE; 1476 l_queueMemRdReq; 1477 sa_setAcks; 1478 o_checkForCompletion; 1479 ra_ackRegionDir; 1480 prd_popRegionQueue; 1481 } 1482 1483 transition(U, {RdBlkSP}, BS_M) {L3TagArrayRead} { 1484 tp_allocateTBEP; 1485 lrp_queueMemRdReqP; 1486 p_popRequestQueue; 1487 } 1488 1489 transition(U, WriteThroughP, BM_M) {L3TagArrayRead} { 1490 tp_allocateTBEP; 1491 wp_sendResponseWBAckP; 1492 lrp_queueMemRdReqP; 1493 p_popRequestQueue; 1494 } 1495 1496 transition(U, {RdBlkMP,AtomicP}, BM_M) {L3TagArrayRead} { 1497 tp_allocateTBEP; 1498 lrp_queueMemRdReqP; 1499 p_popRequestQueue; 1500 } 1501 1502 transition(U, RdBlkP, B_M) {L3TagArrayRead} { 1503 tp_allocateTBEP; 1504 lrp_queueMemRdReqP; 1505 p_popRequestQueue; 1506 } 1507 1508 transition(U, VicDirtyP, BL) {L3TagArrayRead} { 1509 tp_allocateTBEP; 1510 wp_sendResponseWBAckP; 1511 p_popRequestQueue; 1512 } 1513 1514 transition(U, VicCleanP, BL) {L3TagArrayRead} { 1515 tp_allocateTBEP; 1516 wp_sendResponseWBAckP; 1517 p_popRequestQueue; 1518 } 1519 1520 transition(BM_Pm, RdBlkSP, BM_Pm_B) {L3DataArrayWrite} { 1521 sb_sendResponseSBypass; 1522 p_popRequestQueue; 1523 } 1524 1525 transition(BS_Pm, RdBlkSP, BS_Pm_B) {L3DataArrayWrite} { 1526 sb_sendResponseSBypass; 1527 p_popRequestQueue; 1528 } 1529 1530 transition(B_Pm, RdBlkSP, B_Pm_B) {L3DataArrayWrite} { 1531 sb_sendResponseSBypass; 1532 p_popRequestQueue; 1533 } 1534 1535 transition(BP, RdBlkSP, BP_B) {L3DataArrayWrite} { 1536 sb_sendResponseSBypass; 1537 p_popRequestQueue; 1538 } 1539 1540 transition(BM_Pm, RdBlkMP, BM_Pm_B) {L3DataArrayWrite} { 1541 mb_sendResponseMBypass; 1542 p_popRequestQueue; 1543 } 1544 1545 transition(BS_Pm, RdBlkMP, BS_Pm_B) {L3DataArrayWrite} { 1546 mb_sendResponseMBypass; 1547 p_popRequestQueue; 1548 } 1549 1550 transition(B_Pm, RdBlkMP, B_Pm_B) {L3DataArrayWrite} { 1551 mb_sendResponseMBypass; 1552 p_popRequestQueue; 1553 } 1554 1555 transition(BP, RdBlkMP, BP_B) {L3DataArrayWrite} { 1556 mb_sendResponseMBypass; 1557 p_popRequestQueue; 1558 } 1559 1560 transition(BM_Pm, {WriteThroughP,AtomicP}, BM_Pm_B) {L3DataArrayWrite} { 1561 wdp_writeBackDataPrivate; 1562 mbwt_sendResponseWriteThroughBypass; 1563 p_popRequestQueue; 1564 } 1565 1566 transition(BS_Pm, {WriteThroughP,AtomicP}, BS_Pm_B) {L3DataArrayWrite} { 1567 wdp_writeBackDataPrivate; 1568 mbwt_sendResponseWriteThroughBypass; 1569 p_popRequestQueue; 1570 } 1571 1572 transition(B_Pm, {WriteThroughP,AtomicP}, B_Pm_B) {L3DataArrayWrite} { 1573 wdp_writeBackDataPrivate; 1574 mbwt_sendResponseWriteThroughBypass; 1575 p_popRequestQueue; 1576 } 1577 1578 transition(BP, {WriteThroughP,AtomicP}, BP_B) {L3DataArrayWrite} { 1579 wdp_writeBackDataPrivate; 1580 mbwt_sendResponseWriteThroughBypass; 1581 p_popRequestQueue; 1582 } 1583 1584 transition(BM_Pm, RdBlkP, BM_Pm_B) {L3DataArrayWrite} { 1585 esb_sendResponseESBypass; 1586 p_popRequestQueue; 1587 } 1588 1589 transition(BS_Pm, RdBlkP, BS_Pm_B) {L3DataArrayWrite} { 1590 esb_sendResponseESBypass; 1591 p_popRequestQueue; 1592 } 1593 1594 transition(B_Pm, RdBlkP, B_Pm_B) {L3DataArrayWrite}{ 1595 esb_sendResponseESBypass; 1596 p_popRequestQueue; 1597 } 1598 1599 transition(BP, RdBlkP, BP_B) {L3DataArrayWrite}{ 1600 esb_sendResponseESBypass; 1601 p_popRequestQueue; 1602 } 1603 1604 transition(BM_Pm_B, CoreUnblock, BM_Pm) { 1605 wa_wakeUpDependents; 1606 pu_popUnblockQueue; 1607 } 1608 1609 transition(BS_Pm_B, CoreUnblock, BS_Pm) { 1610 wa_wakeUpDependents; 1611 pu_popUnblockQueue; 1612 } 1613 1614 transition(B_Pm_B, CoreUnblock, B_Pm) { 1615 wa_wakeUpDependents; 1616 pu_popUnblockQueue; 1617 } 1618 1619 transition(BP_B, CoreUnblock, BP) { 1620 wa_wakeUpDependents; 1621 pu_popUnblockQueue; 1622 } 1623 1624 transition(BM_Pm_B, UnblockWriteThrough, BM_Pm) { 1625 wa_wakeUpDependents; 1626 pt_popTriggerQueue; 1627 } 1628 1629 transition(BS_Pm_B, UnblockWriteThrough, BS_Pm) { 1630 wa_wakeUpDependents; 1631 pt_popTriggerQueue; 1632 } 1633 1634 transition(B_Pm_B, UnblockWriteThrough, B_Pm) { 1635 wa_wakeUpDependents; 1636 pt_popTriggerQueue; 1637 } 1638 1639 transition(BP_B, UnblockWriteThrough, BP) { 1640 wa_wakeUpDependents; 1641 pt_popTriggerQueue; 1642 } 1643 1644 transition(BM_Pm, VicDirtyP, BM_Pm_BL) { 1645 wp_sendResponseWBAckP; 1646 p_popRequestQueue; 1647 } 1648 1649 transition(BS_Pm, VicDirtyP, BS_Pm_BL) { 1650 wp_sendResponseWBAckP; 1651 p_popRequestQueue; 1652 } 1653 1654 transition(B_Pm, VicDirtyP, B_Pm_BL) { 1655 wp_sendResponseWBAckP; 1656 p_popRequestQueue; 1657 } 1658 1659 transition(BP, VicDirtyP, BP_BL) { 1660 wp_sendResponseWBAckP; 1661 p_popRequestQueue; 1662 } 1663 1664 transition(BM_Pm, VicCleanP, BM_Pm_BL) { 1665 wp_sendResponseWBAckP; 1666 p_popRequestQueue; 1667 } 1668 1669 transition(BS_Pm, VicCleanP, BS_Pm_BL) { 1670 wp_sendResponseWBAckP; 1671 p_popRequestQueue; 1672 } 1673 1674 transition(B_Pm, VicCleanP, B_Pm_BL) { 1675 wp_sendResponseWBAckP; 1676 p_popRequestQueue; 1677 } 1678 1679 transition(BP, VicCleanP, BP_BL) { 1680 wp_sendResponseWBAckP; 1681 p_popRequestQueue; 1682 } 1683 1684 transition(BM_Pm_BL, CPUData, BM_Pm) { 1685 yc_writeCPUDataToTBE; 1686 d_writeDataToMemory; 1687 wa_wakeUpDependents; 1688 pr_popResponseQueue; 1689 } 1690 1691 transition(BS_Pm_BL, CPUData, BS_Pm) { 1692 yc_writeCPUDataToTBE; 1693 d_writeDataToMemory; 1694 wa_wakeUpDependents; 1695 pr_popResponseQueue; 1696 } 1697 1698 transition(B_Pm_BL, CPUData, B_Pm) { 1699 yc_writeCPUDataToTBE; 1700 d_writeDataToMemory; 1701 wa_wakeUpDependents; 1702 pr_popResponseQueue; 1703 } 1704 1705 transition(BP_BL, CPUData, BP) { 1706 yc_writeCPUDataToTBE; 1707 d_writeDataToMemory; 1708 wa_wakeUpDependents; 1709 pr_popResponseQueue; 1710 } 1711 1712 transition({BR, BW, BL}, {VicDirtyP, VicCleanP}) { 1713 st_stallAndWaitRequest; 1714 } 1715 1716 transition({BR, BW, BL}, {VicDirty, VicClean}) { 1717 ww_stallAndWaitRegRequestQueue; 1718 } 1719 1720 transition(BL, CPUData, U) {L3TagArrayWrite, L3DataArrayWrite} { 1721 dt_deallocateTBE; 1722 d_writeDataToMemory; 1723 al_allocateL3Block; 1724 wa_wakeUpDependents; 1725 pr_popResponseQueue; 1726 } 1727 1728 transition(BL, StaleWB, U) {L3TagArrayWrite} { 1729 dt_deallocateTBE; 1730 wa_wakeUpAllDependents; 1731 pr_popResponseQueue; 1732 } 1733 1734 transition({BI, B, BS_M, BM_M, B_M, BP, BS_PM, BM_PM, B_PM, BS_Pm, BM_Pm, B_Pm, BS_Pm_BL, BM_Pm_BL, B_Pm_BL, BP_BL, BS_Pm_B, BM_Pm_B, B_Pm_B, BP_B}, {VicDirty, VicClean}) { 1735 ww_stallAndWaitRegRequestQueue; 1736 } 1737 1738 transition({BI, B, BS_M, BM_M, B_M, BS_PM, BM_PM, B_PM, BS_Pm_BL, BM_Pm_BL, B_Pm_BL, BP_BL, BS_Pm_B, BM_Pm_B, B_Pm_B, BP_B}, {VicDirtyP, VicCleanP}) { 1739 st_stallAndWaitRequest; 1740 } 1741 1742 transition({U, BR, BW, BL, BI, BS_M, BM_M, B_M, BP, BS_PM, BM_PM, B_PM, BS_Pm, BM_Pm, B_Pm, B, BS_Pm_BL, BM_Pm_BL, B_Pm_BL, BP_BL, BS_Pm_B, BM_Pm_B, B_Pm_B, BP_B}, WBAck) { 1743 pm_popMemQueue; 1744 } 1745 1746 transition({U, BR, BW, BL, BI, BS_M, BM_M, B_M, BP, BS_PM, BM_PM, B_PM, BS_Pm, BM_Pm, B_Pm, B, BS_Pm_BL, BM_Pm_BL, B_Pm_BL, BP_BL, BS_Pm_B, BM_Pm_B, B_Pm_B, BP_B}, StaleVicDirtyP) { 1747 rvp_removeVicDirtyIgnore; 1748 wp_sendResponseWBAckP; 1749 p_popRequestQueue; 1750 } 1751 1752 transition({U, BR, BW, BL, BI, BS_M, BM_M, B_M, BP, BS_PM, BM_PM, B_PM, BS_Pm, BM_Pm, B_Pm, B, BS_Pm_BL, BM_Pm_BL, B_Pm_BL, BP_BL, BS_Pm_B, BM_Pm_B, B_Pm_B, BP_B}, StaleVicDirty) { 1753 rv_removeVicDirtyIgnore; 1754 w_sendResponseWBAck; 1755 prd_popRegionQueue; 1756 } 1757 1758 transition(U, VicDirty, BL) {L3TagArrayRead} { 1759 t_allocateTBE; 1760 ra_ackRegionDir; 1761 w_sendResponseWBAck; 1762 prd_popRegionQueue; 1763 } 1764 1765 transition(U, VicClean, BL) {L3TagArrayRead} { 1766 t_allocateTBE; 1767 ra_ackRegionDir; 1768 w_sendResponseWBAck; 1769 prd_popRegionQueue; 1770 } 1771 1772 transition({B, BR}, CoreUnblock, U) { 1773 wa_wakeUpDependents; 1774 pu_popUnblockQueue; 1775 } 1776 1777 transition({B, BR}, UnblockWriteThrough, U) { 1778 wa_wakeUpDependents; 1779 pt_popTriggerQueue; 1780 } 1781 1782 transition(BS_M, MemData, B) {L3TagArrayWrite, L3DataArrayWrite} { 1783 mt_writeMemDataToTBE; 1784 s_sendResponseS; 1785 wd_writeBackData; 1786 alwt_allocateL3BlockOnWT; 1787 dt_deallocateTBE; 1788 pm_popMemQueue; 1789 } 1790 1791 transition(BM_M, MemData, B){L3TagArrayWrite, L3DataArrayWrite} { 1792 mt_writeMemDataToTBE; 1793 m_sendResponseM; 1794 wd_writeBackData; 1795 alwt_allocateL3BlockOnWT; 1796 dt_deallocateTBE; 1797 pm_popMemQueue; 1798 } 1799 1800 transition(B_M, MemData, B){L3TagArrayWrite, L3DataArrayWrite} { 1801 mt_writeMemDataToTBE; 1802 es_sendResponseES; 1803 wd_writeBackData; 1804 alwt_allocateL3BlockOnWT; 1805 dt_deallocateTBE; 1806 pm_popMemQueue; 1807 } 1808 1809 transition(BS_PM, MemData, BS_Pm) {} { 1810 mt_writeMemDataToTBE; 1811 wa_wakeUpDependents; 1812 pm_popMemQueue; 1813 } 1814 1815 transition(BM_PM, MemData, BM_Pm){} { 1816 mt_writeMemDataToTBE; 1817 wa_wakeUpDependents; 1818 pm_popMemQueue; 1819 } 1820 1821 transition(B_PM, MemData, B_Pm){} { 1822 mt_writeMemDataToTBE; 1823 wa_wakeUpDependents; 1824 pm_popMemQueue; 1825 } 1826 1827 transition(BS_M, L3Hit, B) {L3TagArrayWrite, L3DataArrayWrite} { 1828 s_sendResponseS; 1829 wd_writeBackData; 1830 alwt_allocateL3BlockOnWT; 1831 dt_deallocateTBE; 1832 ptl_popTriggerQueue; 1833 } 1834 1835 transition(BM_M, L3Hit, B) {L3TagArrayWrite, L3DataArrayWrite} { 1836 m_sendResponseM; 1837 wd_writeBackData; 1838 alwt_allocateL3BlockOnWT; 1839 dt_deallocateTBE; 1840 ptl_popTriggerQueue; 1841 } 1842 1843 transition(B_M, L3Hit, B) {L3TagArrayWrite, L3DataArrayWrite} { 1844 es_sendResponseES; 1845 wd_writeBackData; 1846 alwt_allocateL3BlockOnWT; 1847 dt_deallocateTBE; 1848 ptl_popTriggerQueue; 1849 } 1850 1851 transition(BS_PM, L3Hit, BS_Pm) { 1852 wa_wakeUpDependents; 1853 ptl_popTriggerQueue; 1854 } 1855 1856 transition(BM_PM, L3Hit, BM_Pm) { 1857 wa_wakeUpDependents; 1858 ptl_popTriggerQueue; 1859 } 1860 1861 transition(B_PM, L3Hit, B_Pm) { 1862 wa_wakeUpDependents; 1863 ptl_popTriggerQueue; 1864 } 1865 1866 transition({BS_PM, BM_PM, B_PM, BS_Pm, BM_Pm, B_Pm, BP, BI}, CPUPrbResp) { 1867 aic_ackInvalidate; 1868 y_writeProbeDataToTBE; 1869 x_decrementAcks; 1870 ont_checkForCompletionNoTrigger; 1871 pr_popResponseQueue; 1872 } 1873 1874 transition({B, B_M, BS_M, BM_M}, {CPUPrbResp, LastCPUPrbResp}) { 1875 z_stall; 1876 } 1877 1878 transition({BS_Pm_BL, BM_Pm_BL, B_Pm_BL, BP_BL, BS_Pm_B, BM_Pm_B, B_Pm_B, BP_B}, {CPUPrbResp, LastCPUPrbResp}) { 1879 // recycling because PrbResponse and data come on the same network 1880 yy_recycleResponseQueue; 1881 } 1882 1883 transition(U, {CPUPrbResp, LastCPUPrbResp}) {L3TagArrayRead, L3DataArrayWrite} { 1884 aic_ackInvalidate; 1885 wdt_writeBackDataInvNoTBE; 1886 ali_allocateL3BlockNoTBE; 1887 pr_popResponseQueue; 1888 } 1889 1890 transition(BL, {CPUPrbResp, LastCPUPrbResp}) {} { 1891 aic_ackInvalidate; 1892 y_writeProbeDataToTBE; 1893 wdi_writeBackDataInv; 1894 ali_allocateL3Block; 1895 pr_popResponseQueue; 1896 } 1897 1898 transition(BS_PM, LastCPUPrbResp, BS_M) { 1899 aic_ackInvalidate; 1900 y_writeProbeDataToTBE; 1901 x_decrementAcks; 1902 ont_checkForCompletionNoTrigger; 1903 pr_popResponseQueue; 1904 } 1905 1906 transition(BS_PM, ProbeAcksComplete, BS_M) {} { 1907 pt_popTriggerQueue; 1908 } 1909 1910 transition(BM_PM, LastCPUPrbResp, BM_M) { 1911 aic_ackInvalidate; 1912 y_writeProbeDataToTBE; 1913 x_decrementAcks; 1914 ont_checkForCompletionNoTrigger; 1915 pr_popResponseQueue; 1916 } 1917 1918 transition(BM_PM, ProbeAcksComplete, BM_M) {} { 1919 pt_popTriggerQueue; 1920 } 1921 1922 transition(B_PM, LastCPUPrbResp, B_M) { 1923 aic_ackInvalidate; 1924 y_writeProbeDataToTBE; 1925 x_decrementAcks; 1926 ont_checkForCompletionNoTrigger; 1927 pr_popResponseQueue; 1928 } 1929 1930 transition(B_PM, ProbeAcksComplete, B_M){} { 1931 pt_popTriggerQueue; 1932 } 1933 1934 transition(BS_Pm, LastCPUPrbResp, B) { 1935 aic_ackInvalidate; 1936 y_writeProbeDataToTBE; 1937 x_decrementAcks; 1938 ont_checkForCompletionNoTrigger; 1939 s_sendResponseS; 1940 wd_writeBackData; 1941 alwt_allocateL3BlockOnWT; 1942 ali_allocateL3Block; 1943 dt_deallocateTBE; 1944 pr_popResponseQueue; 1945 } 1946 1947 transition(BS_Pm, ProbeAcksComplete, B){L3DataArrayWrite, L3TagArrayWrite} { 1948 s_sendResponseS; 1949 wd_writeBackData; 1950 alwt_allocateL3BlockOnWT; 1951 ali_allocateL3Block; 1952 dt_deallocateTBE; 1953 pt_popTriggerQueue; 1954 } 1955 1956 transition(BM_Pm, LastCPUPrbResp, B) { 1957 aic_ackInvalidate; 1958 y_writeProbeDataToTBE; 1959 x_decrementAcks; 1960 ont_checkForCompletionNoTrigger; 1961 m_sendResponseM; 1962 wd_writeBackData; 1963 alwt_allocateL3BlockOnWT; 1964 ali_allocateL3Block; 1965 dt_deallocateTBE; 1966 pr_popResponseQueue; 1967 } 1968 1969 transition(BM_Pm, ProbeAcksComplete, B){L3DataArrayWrite, L3TagArrayWrite} { 1970 m_sendResponseM; 1971 wd_writeBackData; 1972 alwt_allocateL3BlockOnWT; 1973 ali_allocateL3Block; 1974 dt_deallocateTBE; 1975 pt_popTriggerQueue; 1976 } 1977 1978 transition(B_Pm, LastCPUPrbResp, B) { 1979 aic_ackInvalidate; 1980 y_writeProbeDataToTBE; 1981 x_decrementAcks; 1982 ont_checkForCompletionNoTrigger; 1983 es_sendResponseES; 1984 wd_writeBackData; 1985 alwt_allocateL3BlockOnWT; 1986 ali_allocateL3Block; 1987 dt_deallocateTBE; 1988 pr_popResponseQueue; 1989 } 1990 1991 transition(B_Pm, ProbeAcksComplete, B){L3DataArrayWrite, L3TagArrayWrite} { 1992 es_sendResponseES; 1993 wd_writeBackData; 1994 alwt_allocateL3BlockOnWT; 1995 ali_allocateL3Block; 1996 dt_deallocateTBE; 1997 pt_popTriggerQueue; 1998 } 1999 2000 transition(BP, LastCPUPrbResp, B) { 2001 aic_ackInvalidate; 2002 y_writeProbeDataToTBE; 2003 x_decrementAcks; 2004 ont_checkForCompletionNoTrigger; 2005 c_sendResponseCtoD; 2006 wd_writeBackData; 2007 alwt_allocateL3BlockOnWT; 2008 dt_deallocateTBE; 2009 pr_popResponseQueue; 2010 } 2011 2012 transition(BP, ProbeAcksComplete, B){L3TagArrayWrite, L3TagArrayWrite} { 2013 c_sendResponseCtoD; 2014 wd_writeBackData; 2015 alwt_allocateL3BlockOnWT; 2016 dt_deallocateTBE; 2017 pt_popTriggerQueue; 2018 } 2019 2020 transition(BI, LastCPUPrbResp, B) { 2021 aic_ackInvalidate; 2022 y_writeProbeDataToTBE; 2023 x_decrementAcks; 2024 ont_checkForCompletionNoTrigger; 2025 wa_wakeUpDependents; 2026 wdi_writeBackDataInv; 2027 ali_allocateL3Block; 2028 dt_deallocateTBE; 2029 pr_popResponseQueue; 2030 } 2031 2032 transition(BI, ProbeAcksComplete, U) {L3TagArrayWrite, L3DataArrayWrite}{ 2033 wa_wakeUpDependents; 2034 wdi_writeBackDataInv; 2035 ali_allocateL3Block; 2036 dt_deallocateTBE; 2037 pt_popTriggerQueue; 2038 } 2039 2040} 2041