Profiler.hh revision 7832:de7601e6e19d
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 This file has been modified by Kevin Moore and Dan Nussbaum of the 31 Scalable Systems Research Group at Sun Microsystems Laboratories 32 (http://research.sun.com/scalable/) to support the Adaptive 33 Transactional Memory Test Platform (ATMTP). 34 35 Please send email to atmtp-interest@sun.com with feedback, questions, or 36 to request future announcements about ATMTP. 37 38 ---------------------------------------------------------------------- 39 40 File modification date: 2008-02-23 41 42 ---------------------------------------------------------------------- 43*/ 44 45#ifndef __MEM_RUBY_PROFILER_PROFILER_HH__ 46#define __MEM_RUBY_PROFILER_PROFILER_HH__ 47 48#include <iostream> 49#include <map> 50#include <string> 51#include <vector> 52 53#include "base/hashmap.hh" 54#include "mem/protocol/AccessModeType.hh" 55#include "mem/protocol/AccessType.hh" 56#include "mem/protocol/CacheRequestType.hh" 57#include "mem/protocol/GenericMachineType.hh" 58#include "mem/protocol/GenericRequestType.hh" 59#include "mem/protocol/PrefetchBit.hh" 60#include "mem/ruby/common/Address.hh" 61#include "mem/ruby/common/Consumer.hh" 62#include "mem/ruby/common/Global.hh" 63#include "mem/ruby/common/Histogram.hh" 64#include "mem/ruby/common/Set.hh" 65#include "mem/ruby/libruby.hh" 66#include "mem/ruby/system/MachineID.hh" 67#include "mem/ruby/system/MemoryControl.hh" 68#include "mem/ruby/system/NodeID.hh" 69#include "params/RubyProfiler.hh" 70#include "sim/sim_object.hh" 71 72class CacheMsg; 73class AddressProfiler; 74 75class Profiler : public SimObject, public Consumer 76{ 77 public: 78 typedef RubyProfilerParams Params; 79 Profiler(const Params *); 80 ~Profiler(); 81 82 void wakeup(); 83 84 void setPeriodicStatsFile(const std::string& filename); 85 void setPeriodicStatsInterval(integer_t period); 86 87 void printStats(std::ostream& out, bool short_stats=false); 88 void printShortStats(std::ostream& out) { printStats(out, true); } 89 void printTraceStats(std::ostream& out) const; 90 void clearStats(); 91 void printConfig(std::ostream& out) const; 92 void printResourceUsage(std::ostream& out) const; 93 94 AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; } 95 AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; } 96 97 void addAddressTraceSample(const CacheMsg& msg, NodeID id); 98 99 void profileRequest(const std::string& requestStr); 100 void profileSharing(const Address& addr, AccessType type, 101 NodeID requestor, const Set& sharers, 102 const Set& owner); 103 104 void profileMulticastRetry(const Address& addr, int count); 105 106 void profileFilterAction(int action); 107 108 void profileConflictingRequests(const Address& addr); 109 110 void 111 profileOutstandingRequest(int outstanding) 112 { 113 m_outstanding_requests.add(outstanding); 114 } 115 116 void 117 profileOutstandingPersistentRequest(int outstanding) 118 { 119 m_outstanding_persistent_requests.add(outstanding); 120 } 121 122 void 123 profileAverageLatencyEstimate(int latency) 124 { 125 m_average_latency_estimate.add(latency); 126 } 127 128 void recordPrediction(bool wasGood, bool wasPredicted); 129 130 void startTransaction(int cpu); 131 void endTransaction(int cpu); 132 void profilePFWait(Time waitTime); 133 134 void controllerBusy(MachineID machID); 135 void bankBusy(); 136 137 void missLatency(Time t, 138 RubyRequestType type, 139 const GenericMachineType respondingMach); 140 141 void missLatencyWcc(Time issuedTime, 142 Time initialRequestTime, 143 Time forwardRequestTime, 144 Time firstResponseTime, 145 Time completionTime); 146 147 void missLatencyDir(Time issuedTime, 148 Time initialRequestTime, 149 Time forwardRequestTime, 150 Time firstResponseTime, 151 Time completionTime); 152 153 void swPrefetchLatency(Time t, 154 CacheRequestType type, 155 const GenericMachineType respondingMach); 156 157 void sequencerRequests(int num) { m_sequencer_requests.add(num); } 158 159 void profileMsgDelay(int virtualNetwork, int delayCycles); 160 161 void print(std::ostream& out) const; 162 163 void rubyWatch(int proc); 164 bool watchAddress(Address addr); 165 166 // return Ruby's start time 167 Time 168 getRubyStartTime() 169 { 170 return m_ruby_start; 171 } 172 173 // added by SS 174 bool getHotLines() { return m_hot_lines; } 175 bool getAllInstructions() { return m_all_instructions; } 176 177 private: 178 // Private copy constructor and assignment operator 179 Profiler(const Profiler& obj); 180 Profiler& operator=(const Profiler& obj); 181 182 AddressProfiler* m_address_profiler_ptr; 183 AddressProfiler* m_inst_profiler_ptr; 184 185 std::vector<int64> m_instructions_executed_at_start; 186 std::vector<int64> m_cycles_executed_at_start; 187 188 std::ostream* m_periodic_output_file_ptr; 189 integer_t m_stats_period; 190 191 Time m_ruby_start; 192 time_t m_real_time_start_time; 193 194 std::vector<std::vector<integer_t> > m_busyControllerCount; 195 integer_t m_busyBankCount; 196 Histogram m_multicast_retry_histogram; 197 198 Histogram m_filter_action_histogram; 199 Histogram m_tbeProfile; 200 201 Histogram m_sequencer_requests; 202 Histogram m_read_sharing_histogram; 203 Histogram m_write_sharing_histogram; 204 Histogram m_all_sharing_histogram; 205 int64 m_cache_to_cache; 206 int64 m_memory_to_cache; 207 208 Histogram m_prefetchWaitHistogram; 209 210 std::vector<Histogram> m_missLatencyHistograms; 211 std::vector<Histogram> m_machLatencyHistograms; 212 std::vector< std::vector<Histogram> > m_missMachLatencyHistograms; 213 Histogram m_wCCIssueToInitialRequestHistogram; 214 Histogram m_wCCInitialRequestToForwardRequestHistogram; 215 Histogram m_wCCForwardRequestToFirstResponseHistogram; 216 Histogram m_wCCFirstResponseToCompleteHistogram; 217 int64 m_wCCIncompleteTimes; 218 Histogram m_dirIssueToInitialRequestHistogram; 219 Histogram m_dirInitialRequestToForwardRequestHistogram; 220 Histogram m_dirForwardRequestToFirstResponseHistogram; 221 Histogram m_dirFirstResponseToCompleteHistogram; 222 int64 m_dirIncompleteTimes; 223 224 Histogram m_allMissLatencyHistogram; 225 226 Histogram m_allSWPrefetchLatencyHistogram; 227 Histogram m_SWPrefetchL2MissLatencyHistogram; 228 std::vector<Histogram> m_SWPrefetchLatencyHistograms; 229 std::vector<Histogram> m_SWPrefetchMachLatencyHistograms; 230 231 Histogram m_delayedCyclesHistogram; 232 Histogram m_delayedCyclesNonPFHistogram; 233 std::vector<Histogram> m_delayedCyclesVCHistograms; 234 235 Histogram m_outstanding_requests; 236 Histogram m_outstanding_persistent_requests; 237 238 Histogram m_average_latency_estimate; 239 240 m5::hash_set<Address> m_watch_address_set; 241 // counts all initiated cache request including PUTs 242 int m_requests; 243 std::map<std::string, int> m_requestProfileMap; 244 245 //added by SS 246 bool m_hot_lines; 247 bool m_all_instructions; 248 249 int m_num_of_sequencers; 250}; 251 252inline std::ostream& 253operator<<(std::ostream& out, const Profiler& obj) 254{ 255 obj.print(out); 256 out << std::flush; 257 return out; 258} 259 260#endif // __MEM_RUBY_PROFILER_PROFILER_HH__ 261 262 263