Profiler.cc revision 9746:7d235b709425
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 This file has been modified by Kevin Moore and Dan Nussbaum of the 31 Scalable Systems Research Group at Sun Microsystems Laboratories 32 (http://research.sun.com/scalable/) to support the Adaptive 33 Transactional Memory Test Platform (ATMTP). 34 35 Please send email to atmtp-interest@sun.com with feedback, questions, or 36 to request future announcements about ATMTP. 37 38 ---------------------------------------------------------------------- 39 40 File modification date: 2008-02-23 41 42 ---------------------------------------------------------------------- 43*/ 44 45// Allows use of times() library call, which determines virtual runtime 46#include <sys/resource.h> 47#include <sys/times.h> 48#include <sys/types.h> 49#include <unistd.h> 50 51#include <algorithm> 52#include <fstream> 53 54#include "base/stl_helpers.hh" 55#include "base/str.hh" 56#include "mem/protocol/MachineType.hh" 57#include "mem/protocol/RubyRequest.hh" 58#include "mem/ruby/network/Network.hh" 59#include "mem/ruby/profiler/AddressProfiler.hh" 60#include "mem/ruby/profiler/Profiler.hh" 61#include "mem/ruby/system/Sequencer.hh" 62#include "mem/ruby/system/System.hh" 63 64using namespace std; 65using m5::stl_helpers::operator<<; 66 67static double process_memory_total(); 68static double process_memory_resident(); 69 70Profiler::Profiler(const Params *p) 71 : SimObject(p) 72{ 73 m_inst_profiler_ptr = NULL; 74 m_address_profiler_ptr = NULL; 75 m_real_time_start_time = time(NULL); // Not reset in clearStats() 76 77 m_hot_lines = p->hot_lines; 78 m_all_instructions = p->all_instructions; 79 80 m_num_of_sequencers = p->num_of_sequencers; 81 82 m_hot_lines = false; 83 m_all_instructions = false; 84 85 m_address_profiler_ptr = new AddressProfiler(m_num_of_sequencers); 86 m_address_profiler_ptr->setHotLines(m_hot_lines); 87 m_address_profiler_ptr->setAllInstructions(m_all_instructions); 88 89 if (m_all_instructions) { 90 m_inst_profiler_ptr = new AddressProfiler(m_num_of_sequencers); 91 m_inst_profiler_ptr->setHotLines(m_hot_lines); 92 m_inst_profiler_ptr->setAllInstructions(m_all_instructions); 93 } 94 95 p->ruby_system->registerProfiler(this); 96} 97 98Profiler::~Profiler() 99{ 100} 101 102void 103Profiler::print(ostream& out) const 104{ 105 out << "[Profiler]"; 106} 107 108void 109Profiler::printRequestProfile(ostream &out) const 110{ 111 out << "Request vs. RubySystem State Profile" << endl; 112 out << "--------------------------------" << endl; 113 out << endl; 114 115 map<string, uint64_t> m_requestProfileMap; 116 uint64_t m_requests = 0; 117 118 for (uint32_t i = 0; i < MachineType_NUM; i++) { 119 for (map<uint32_t, AbstractController*>::iterator it = 120 g_abs_controls[i].begin(); 121 it != g_abs_controls[i].end(); ++it) { 122 123 AbstractController *ctr = (*it).second; 124 map<string, uint64_t> mp = ctr->getRequestProfileMap(); 125 126 for (map<string, uint64_t>::iterator jt = mp.begin(); 127 jt != mp.end(); ++jt) { 128 129 map<string, uint64_t>::iterator kt = 130 m_requestProfileMap.find((*jt).first); 131 if (kt != m_requestProfileMap.end()) { 132 (*kt).second += (*jt).second; 133 } else { 134 m_requestProfileMap[(*jt).first] = (*jt).second; 135 } 136 } 137 138 m_requests += ctr->getRequestCount(); 139 } 140 } 141 142 map<string, uint64_t>::const_iterator i = m_requestProfileMap.begin(); 143 map<string, uint64_t>::const_iterator end = m_requestProfileMap.end(); 144 for (; i != end; ++i) { 145 const string &key = i->first; 146 uint64_t count = i->second; 147 148 double percent = (100.0 * double(count)) / double(m_requests); 149 vector<string> items; 150 tokenize(items, key, ':'); 151 vector<string>::iterator j = items.begin(); 152 vector<string>::iterator end = items.end(); 153 for (; j != end; ++i) 154 out << setw(10) << *j; 155 out << setw(11) << count; 156 out << setw(14) << percent << endl; 157 } 158 out << endl; 159} 160 161void 162Profiler::printDelayProfile(ostream &out) const 163{ 164 out << "Message Delayed Cycles" << endl; 165 out << "----------------------" << endl; 166 167 uint32_t numVNets = Network::getNumberOfVirtualNetworks(); 168 Histogram delayHistogram; 169 std::vector<Histogram> delayVCHistogram(numVNets); 170 171 for (uint32_t i = 0; i < MachineType_NUM; i++) { 172 for (map<uint32_t, AbstractController*>::iterator it = 173 g_abs_controls[i].begin(); 174 it != g_abs_controls[i].end(); ++it) { 175 176 AbstractController *ctr = (*it).second; 177 delayHistogram.add(ctr->getDelayHist()); 178 179 for (uint32_t i = 0; i < numVNets; i++) { 180 delayVCHistogram[i].add(ctr->getDelayVCHist(i)); 181 } 182 } 183 } 184 185 out << "Total_delay_cycles: " << delayHistogram << endl; 186 187 for (int i = 0; i < numVNets; i++) { 188 out << " virtual_network_" << i << "_delay_cycles: " 189 << delayVCHistogram[i] << endl; 190 } 191} 192 193void 194Profiler::printOutstandingReqProfile(ostream &out) const 195{ 196 Histogram sequencerRequests; 197 198 for (uint32_t i = 0; i < MachineType_NUM; i++) { 199 for (map<uint32_t, AbstractController*>::iterator it = 200 g_abs_controls[i].begin(); 201 it != g_abs_controls[i].end(); ++it) { 202 203 AbstractController *ctr = (*it).second; 204 Sequencer *seq = ctr->getSequencer(); 205 if (seq != NULL) { 206 sequencerRequests.add(seq->getOutstandReqHist()); 207 } 208 } 209 } 210 211 out << "sequencer_requests_outstanding: " 212 << sequencerRequests << endl; 213} 214 215void 216Profiler::printStats(ostream& out, bool short_stats) 217{ 218 out << endl; 219 if (short_stats) { 220 out << "SHORT "; 221 } 222 out << "Profiler Stats" << endl; 223 out << "--------------" << endl; 224 225 time_t real_time_current = time(NULL); 226 double seconds = difftime(real_time_current, m_real_time_start_time); 227 double minutes = seconds / 60.0; 228 double hours = minutes / 60.0; 229 double days = hours / 24.0; 230 Cycles ruby_cycles = g_system_ptr->curCycle()-m_ruby_start; 231 232 if (!short_stats) { 233 out << "Elapsed_time_in_seconds: " << seconds << endl; 234 out << "Elapsed_time_in_minutes: " << minutes << endl; 235 out << "Elapsed_time_in_hours: " << hours << endl; 236 out << "Elapsed_time_in_days: " << days << endl; 237 out << endl; 238 } 239 240 // print the virtual runtimes as well 241 struct tms vtime; 242 times(&vtime); 243 seconds = (vtime.tms_utime + vtime.tms_stime) / 100.0; 244 minutes = seconds / 60.0; 245 hours = minutes / 60.0; 246 days = hours / 24.0; 247 out << "Virtual_time_in_seconds: " << seconds << endl; 248 out << "Virtual_time_in_minutes: " << minutes << endl; 249 out << "Virtual_time_in_hours: " << hours << endl; 250 out << "Virtual_time_in_days: " << days << endl; 251 out << endl; 252 253 out << "Ruby_current_time: " << g_system_ptr->curCycle() << endl; 254 out << "Ruby_start_time: " << m_ruby_start << endl; 255 out << "Ruby_cycles: " << ruby_cycles << endl; 256 out << endl; 257 258 if (!short_stats) { 259 out << "mbytes_resident: " << process_memory_resident() << endl; 260 out << "mbytes_total: " << process_memory_total() << endl; 261 if (process_memory_total() > 0) { 262 out << "resident_ratio: " 263 << process_memory_resident()/process_memory_total() << endl; 264 } 265 out << endl; 266 } 267 268 vector<int64_t> perProcCycleCount(m_num_of_sequencers); 269 270 for (int i = 0; i < m_num_of_sequencers; i++) { 271 perProcCycleCount[i] = 272 g_system_ptr->curCycle() - m_cycles_executed_at_start[i] + 1; 273 // The +1 allows us to avoid division by zero 274 } 275 276 out << "ruby_cycles_executed: " << perProcCycleCount << endl; 277 278 out << endl; 279 280 if (!short_stats) { 281 out << "Busy Controller Counts:" << endl; 282 for (uint32_t i = 0; i < MachineType_NUM; i++) { 283 uint32_t size = MachineType_base_count((MachineType)i); 284 285 for (uint32_t j = 0; j < size; j++) { 286 MachineID machID; 287 machID.type = (MachineType)i; 288 machID.num = j; 289 290 AbstractController *ctr = 291 (*(g_abs_controls[i].find(j))).second; 292 out << machID << ":" << ctr->getFullyBusyCycles() << " "; 293 if ((j + 1) % 8 == 0) { 294 out << endl; 295 } 296 } 297 out << endl; 298 } 299 out << endl; 300 301 out << "Busy Bank Count:" << m_busyBankCount << endl; 302 out << endl; 303 304 printOutstandingReqProfile(out); 305 out << endl; 306 } 307 308 if (!short_stats) { 309 out << "All Non-Zero Cycle Demand Cache Accesses" << endl; 310 out << "----------------------------------------" << endl; 311 out << "miss_latency: " << m_allMissLatencyHistogram << endl; 312 for (int i = 0; i < m_missLatencyHistograms.size(); i++) { 313 if (m_missLatencyHistograms[i].size() > 0) { 314 out << "miss_latency_" << RubyRequestType(i) << ": " 315 << m_missLatencyHistograms[i] << endl; 316 } 317 } 318 for (int i = 0; i < m_machLatencyHistograms.size(); i++) { 319 if (m_machLatencyHistograms[i].size() > 0) { 320 out << "miss_latency_" << GenericMachineType(i) << ": " 321 << m_machLatencyHistograms[i] << endl; 322 } 323 } 324 325 out << "miss_latency_wCC_issue_to_initial_request: " 326 << m_wCCIssueToInitialRequestHistogram << endl; 327 out << "miss_latency_wCC_initial_forward_request: " 328 << m_wCCInitialRequestToForwardRequestHistogram << endl; 329 out << "miss_latency_wCC_forward_to_first_response: " 330 << m_wCCForwardRequestToFirstResponseHistogram << endl; 331 out << "miss_latency_wCC_first_response_to_completion: " 332 << m_wCCFirstResponseToCompleteHistogram << endl; 333 out << "imcomplete_wCC_Times: " << m_wCCIncompleteTimes << endl; 334 out << "miss_latency_dir_issue_to_initial_request: " 335 << m_dirIssueToInitialRequestHistogram << endl; 336 out << "miss_latency_dir_initial_forward_request: " 337 << m_dirInitialRequestToForwardRequestHistogram << endl; 338 out << "miss_latency_dir_forward_to_first_response: " 339 << m_dirForwardRequestToFirstResponseHistogram << endl; 340 out << "miss_latency_dir_first_response_to_completion: " 341 << m_dirFirstResponseToCompleteHistogram << endl; 342 out << "imcomplete_dir_Times: " << m_dirIncompleteTimes << endl; 343 344 for (int i = 0; i < m_missMachLatencyHistograms.size(); i++) { 345 for (int j = 0; j < m_missMachLatencyHistograms[i].size(); j++) { 346 if (m_missMachLatencyHistograms[i][j].size() > 0) { 347 out << "miss_latency_" << RubyRequestType(i) 348 << "_" << GenericMachineType(j) << ": " 349 << m_missMachLatencyHistograms[i][j] << endl; 350 } 351 } 352 } 353 354 out << endl; 355 356 out << "All Non-Zero Cycle SW Prefetch Requests" << endl; 357 out << "------------------------------------" << endl; 358 out << "prefetch_latency: " << m_allSWPrefetchLatencyHistogram << endl; 359 for (int i = 0; i < m_SWPrefetchLatencyHistograms.size(); i++) { 360 if (m_SWPrefetchLatencyHistograms[i].size() > 0) { 361 out << "prefetch_latency_" << RubyRequestType(i) << ": " 362 << m_SWPrefetchLatencyHistograms[i] << endl; 363 } 364 } 365 for (int i = 0; i < m_SWPrefetchMachLatencyHistograms.size(); i++) { 366 if (m_SWPrefetchMachLatencyHistograms[i].size() > 0) { 367 out << "prefetch_latency_" << GenericMachineType(i) << ": " 368 << m_SWPrefetchMachLatencyHistograms[i] << endl; 369 } 370 } 371 out << "prefetch_latency_L2Miss:" 372 << m_SWPrefetchL2MissLatencyHistogram << endl; 373 374 if (m_all_sharing_histogram.size() > 0) { 375 out << "all_sharing: " << m_all_sharing_histogram << endl; 376 out << "read_sharing: " << m_read_sharing_histogram << endl; 377 out << "write_sharing: " << m_write_sharing_histogram << endl; 378 379 out << "all_sharing_percent: "; 380 m_all_sharing_histogram.printPercent(out); 381 out << endl; 382 383 out << "read_sharing_percent: "; 384 m_read_sharing_histogram.printPercent(out); 385 out << endl; 386 387 out << "write_sharing_percent: "; 388 m_write_sharing_histogram.printPercent(out); 389 out << endl; 390 391 int64 total_miss = m_cache_to_cache + m_memory_to_cache; 392 out << "all_misses: " << total_miss << endl; 393 out << "cache_to_cache_misses: " << m_cache_to_cache << endl; 394 out << "memory_to_cache_misses: " << m_memory_to_cache << endl; 395 out << "cache_to_cache_percent: " 396 << 100.0 * (double(m_cache_to_cache) / double(total_miss)) 397 << endl; 398 out << "memory_to_cache_percent: " 399 << 100.0 * (double(m_memory_to_cache) / double(total_miss)) 400 << endl; 401 out << endl; 402 } 403 404 printRequestProfile(out); 405 406 out << "filter_action: " << m_filter_action_histogram << endl; 407 408 if (!m_all_instructions) { 409 m_address_profiler_ptr->printStats(out); 410 } 411 412 if (m_all_instructions) { 413 m_inst_profiler_ptr->printStats(out); 414 } 415 416 out << endl; 417 printDelayProfile(out); 418 printResourceUsage(out); 419 } 420} 421 422void 423Profiler::printResourceUsage(ostream& out) const 424{ 425 out << endl; 426 out << "Resource Usage" << endl; 427 out << "--------------" << endl; 428 429 int64_t pagesize = getpagesize(); // page size in bytes 430 out << "page_size: " << pagesize << endl; 431 432 rusage usage; 433 getrusage (RUSAGE_SELF, &usage); 434 435 out << "user_time: " << usage.ru_utime.tv_sec << endl; 436 out << "system_time: " << usage.ru_stime.tv_sec << endl; 437 out << "page_reclaims: " << usage.ru_minflt << endl; 438 out << "page_faults: " << usage.ru_majflt << endl; 439 out << "swaps: " << usage.ru_nswap << endl; 440 out << "block_inputs: " << usage.ru_inblock << endl; 441 out << "block_outputs: " << usage.ru_oublock << endl; 442} 443 444void 445Profiler::clearStats() 446{ 447 m_ruby_start = g_system_ptr->curCycle(); 448 m_real_time_start_time = time(NULL); 449 450 m_cycles_executed_at_start.resize(m_num_of_sequencers); 451 for (int i = 0; i < m_num_of_sequencers; i++) { 452 m_cycles_executed_at_start[i] = g_system_ptr->curCycle(); 453 } 454 455 m_busyBankCount = 0; 456 457 m_missLatencyHistograms.resize(RubyRequestType_NUM); 458 for (int i = 0; i < m_missLatencyHistograms.size(); i++) { 459 m_missLatencyHistograms[i].clear(200); 460 } 461 m_machLatencyHistograms.resize(GenericMachineType_NUM+1); 462 for (int i = 0; i < m_machLatencyHistograms.size(); i++) { 463 m_machLatencyHistograms[i].clear(200); 464 } 465 m_missMachLatencyHistograms.resize(RubyRequestType_NUM); 466 for (int i = 0; i < m_missLatencyHistograms.size(); i++) { 467 m_missMachLatencyHistograms[i].resize(GenericMachineType_NUM+1); 468 for (int j = 0; j < m_missMachLatencyHistograms[i].size(); j++) { 469 m_missMachLatencyHistograms[i][j].clear(200); 470 } 471 } 472 m_allMissLatencyHistogram.clear(200); 473 m_wCCIssueToInitialRequestHistogram.clear(200); 474 m_wCCInitialRequestToForwardRequestHistogram.clear(200); 475 m_wCCForwardRequestToFirstResponseHistogram.clear(200); 476 m_wCCFirstResponseToCompleteHistogram.clear(200); 477 m_wCCIncompleteTimes = 0; 478 m_dirIssueToInitialRequestHistogram.clear(200); 479 m_dirInitialRequestToForwardRequestHistogram.clear(200); 480 m_dirForwardRequestToFirstResponseHistogram.clear(200); 481 m_dirFirstResponseToCompleteHistogram.clear(200); 482 m_dirIncompleteTimes = 0; 483 484 m_SWPrefetchLatencyHistograms.resize(RubyRequestType_NUM); 485 for (int i = 0; i < m_SWPrefetchLatencyHistograms.size(); i++) { 486 m_SWPrefetchLatencyHistograms[i].clear(200); 487 } 488 m_SWPrefetchMachLatencyHistograms.resize(GenericMachineType_NUM+1); 489 for (int i = 0; i < m_SWPrefetchMachLatencyHistograms.size(); i++) { 490 m_SWPrefetchMachLatencyHistograms[i].clear(200); 491 } 492 m_allSWPrefetchLatencyHistogram.clear(200); 493 494 m_read_sharing_histogram.clear(); 495 m_write_sharing_histogram.clear(); 496 m_all_sharing_histogram.clear(); 497 m_cache_to_cache = 0; 498 m_memory_to_cache = 0; 499 500 // update the start time 501 m_ruby_start = g_system_ptr->curCycle(); 502} 503 504void 505Profiler::addAddressTraceSample(const RubyRequest& msg, NodeID id) 506{ 507 if (msg.getType() != RubyRequestType_IFETCH) { 508 // Note: The following line should be commented out if you 509 // want to use the special profiling that is part of the GS320 510 // protocol 511 512 // NOTE: Unless PROFILE_HOT_LINES is enabled, nothing will be 513 // profiled by the AddressProfiler 514 m_address_profiler_ptr-> 515 addTraceSample(msg.getLineAddress(), msg.getProgramCounter(), 516 msg.getType(), msg.getAccessMode(), id, false); 517 } 518} 519 520void 521Profiler::profileSharing(const Address& addr, AccessType type, 522 NodeID requestor, const Set& sharers, 523 const Set& owner) 524{ 525 Set set_contacted(owner); 526 if (type == AccessType_Write) { 527 set_contacted.addSet(sharers); 528 } 529 set_contacted.remove(requestor); 530 int number_contacted = set_contacted.count(); 531 532 if (type == AccessType_Write) { 533 m_write_sharing_histogram.add(number_contacted); 534 } else { 535 m_read_sharing_histogram.add(number_contacted); 536 } 537 m_all_sharing_histogram.add(number_contacted); 538 539 if (number_contacted == 0) { 540 m_memory_to_cache++; 541 } else { 542 m_cache_to_cache++; 543 } 544} 545 546void 547Profiler::profilePFWait(Cycles waitTime) 548{ 549 m_prefetchWaitHistogram.add(waitTime); 550} 551 552void 553Profiler::bankBusy() 554{ 555 m_busyBankCount++; 556} 557 558// non-zero cycle demand request 559void 560Profiler::missLatency(Cycles cycles, 561 RubyRequestType type, 562 const GenericMachineType respondingMach) 563{ 564 m_allMissLatencyHistogram.add(cycles); 565 m_missLatencyHistograms[type].add(cycles); 566 m_machLatencyHistograms[respondingMach].add(cycles); 567 m_missMachLatencyHistograms[type][respondingMach].add(cycles); 568} 569 570void 571Profiler::missLatencyWcc(Cycles issuedTime, 572 Cycles initialRequestTime, 573 Cycles forwardRequestTime, 574 Cycles firstResponseTime, 575 Cycles completionTime) 576{ 577 if ((issuedTime <= initialRequestTime) && 578 (initialRequestTime <= forwardRequestTime) && 579 (forwardRequestTime <= firstResponseTime) && 580 (firstResponseTime <= completionTime)) { 581 m_wCCIssueToInitialRequestHistogram.add(initialRequestTime - issuedTime); 582 583 m_wCCInitialRequestToForwardRequestHistogram.add(forwardRequestTime - 584 initialRequestTime); 585 586 m_wCCForwardRequestToFirstResponseHistogram.add(firstResponseTime - 587 forwardRequestTime); 588 589 m_wCCFirstResponseToCompleteHistogram.add(completionTime - 590 firstResponseTime); 591 } else { 592 m_wCCIncompleteTimes++; 593 } 594} 595 596void 597Profiler::missLatencyDir(Cycles issuedTime, 598 Cycles initialRequestTime, 599 Cycles forwardRequestTime, 600 Cycles firstResponseTime, 601 Cycles completionTime) 602{ 603 if ((issuedTime <= initialRequestTime) && 604 (initialRequestTime <= forwardRequestTime) && 605 (forwardRequestTime <= firstResponseTime) && 606 (firstResponseTime <= completionTime)) { 607 m_dirIssueToInitialRequestHistogram.add(initialRequestTime - issuedTime); 608 609 m_dirInitialRequestToForwardRequestHistogram.add(forwardRequestTime - 610 initialRequestTime); 611 612 m_dirForwardRequestToFirstResponseHistogram.add(firstResponseTime - 613 forwardRequestTime); 614 615 m_dirFirstResponseToCompleteHistogram.add(completionTime - 616 firstResponseTime); 617 } else { 618 m_dirIncompleteTimes++; 619 } 620} 621 622// non-zero cycle prefetch request 623void 624Profiler::swPrefetchLatency(Cycles cycles, RubyRequestType type, 625 const GenericMachineType respondingMach) 626{ 627 m_allSWPrefetchLatencyHistogram.add(cycles); 628 m_SWPrefetchLatencyHistograms[type].add(cycles); 629 m_SWPrefetchMachLatencyHistograms[respondingMach].add(cycles); 630 631 if (respondingMach == GenericMachineType_Directory || 632 respondingMach == GenericMachineType_NUM) { 633 m_SWPrefetchL2MissLatencyHistogram.add(cycles); 634 } 635} 636 637// Helper function 638static double 639process_memory_total() 640{ 641 // 4kB page size, 1024*1024 bytes per MB, 642 const double MULTIPLIER = 4096.0 / (1024.0 * 1024.0); 643 ifstream proc_file; 644 proc_file.open("/proc/self/statm"); 645 int total_size_in_pages = 0; 646 int res_size_in_pages = 0; 647 proc_file >> total_size_in_pages; 648 proc_file >> res_size_in_pages; 649 return double(total_size_in_pages) * MULTIPLIER; // size in megabytes 650} 651 652static double 653process_memory_resident() 654{ 655 // 4kB page size, 1024*1024 bytes per MB, 656 const double MULTIPLIER = 4096.0 / (1024.0 * 1024.0); 657 ifstream proc_file; 658 proc_file.open("/proc/self/statm"); 659 int total_size_in_pages = 0; 660 int res_size_in_pages = 0; 661 proc_file >> total_size_in_pages; 662 proc_file >> res_size_in_pages; 663 return double(res_size_in_pages) * MULTIPLIER; // size in megabytes 664} 665 666void 667Profiler::rubyWatch(int id) 668{ 669 uint64 tr = 0; 670 Address watch_address = Address(tr); 671 672 DPRINTFN("%7s %3s RUBY WATCH %d\n", g_system_ptr->curCycle(), id, 673 watch_address); 674 675 // don't care about success or failure 676 m_watch_address_set.insert(watch_address); 677} 678 679bool 680Profiler::watchAddress(Address addr) 681{ 682 return m_watch_address_set.count(addr) > 0; 683} 684 685Profiler * 686RubyProfilerParams::create() 687{ 688 return new Profiler(this); 689} 690