Switch.hh revision 9230:33eb3c8a98b9 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The actual modelled switch. It use the perfect switch and a
31 * Throttle object to control and bandwidth and timing *only for the
32 * output port*. So here we have un-realistic modelling, since the
33 * order of PerfectSwitch and Throttle objects get woke up affect the
34 * message timing. A more accurate model would be having two set of
35 * system states, one for this cycle, one for next cycle. And on the
36 * cycle boundary swap the two set of states.
37 */
38
39#ifndef __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
40#define __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
41
42#include <iostream>
43#include <vector>
44
45class MessageBuffer;
46class PerfectSwitch;
47class NetDest;
48class SimpleNetwork;
49class Throttle;
50
51class Switch
52{
53  public:
54    Switch(SwitchID sid, SimpleNetwork* network_ptr);
55    ~Switch();
56
57    void addInPort(const std::vector<MessageBuffer*>& in);
58    void addOutPort(const std::vector<MessageBuffer*>& out,
59        const NetDest& routing_table_entry, int link_latency,
60        int bw_multiplier);
61    const Throttle* getThrottle(LinkID link_number) const;
62    const std::vector<Throttle*>* getThrottles() const;
63    void clearRoutingTables();
64    void clearBuffers();
65    void reconfigureOutPort(const NetDest& routing_table_entry);
66
67    void printStats(std::ostream& out) const;
68    void clearStats();
69    void print(std::ostream& out) const;
70
71  private:
72    // Private copy constructor and assignment operator
73    Switch(const Switch& obj);
74    Switch& operator=(const Switch& obj);
75
76    PerfectSwitch* m_perfect_switch_ptr;
77    SimpleNetwork* m_network_ptr;
78    std::vector<Throttle*> m_throttles;
79    std::vector<MessageBuffer*> m_buffers_to_free;
80    SwitchID m_switch_id;
81};
82
83inline std::ostream&
84operator<<(std::ostream& out, const Switch& obj)
85{
86    obj.print(out);
87    out << std::flush;
88    return out;
89}
90
91#endif // __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
92