Switch.hh revision 8259:36987780169e
16892SBrad.Beckmann@amd.com/* 26892SBrad.Beckmann@amd.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36892SBrad.Beckmann@amd.com * All rights reserved. 46892SBrad.Beckmann@amd.com * 56892SBrad.Beckmann@amd.com * Redistribution and use in source and binary forms, with or without 66892SBrad.Beckmann@amd.com * modification, are permitted provided that the following conditions are 76892SBrad.Beckmann@amd.com * met: redistributions of source code must retain the above copyright 86892SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer; 96892SBrad.Beckmann@amd.com * redistributions in binary form must reproduce the above copyright 106892SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer in the 116892SBrad.Beckmann@amd.com * documentation and/or other materials provided with the distribution; 126892SBrad.Beckmann@amd.com * neither the name of the copyright holders nor the names of its 136892SBrad.Beckmann@amd.com * contributors may be used to endorse or promote products derived from 146892SBrad.Beckmann@amd.com * this software without specific prior written permission. 156892SBrad.Beckmann@amd.com * 166892SBrad.Beckmann@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176892SBrad.Beckmann@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186892SBrad.Beckmann@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196892SBrad.Beckmann@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206892SBrad.Beckmann@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216892SBrad.Beckmann@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226892SBrad.Beckmann@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236892SBrad.Beckmann@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246892SBrad.Beckmann@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256892SBrad.Beckmann@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266892SBrad.Beckmann@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276892SBrad.Beckmann@amd.com */ 286892SBrad.Beckmann@amd.com 296892SBrad.Beckmann@amd.com/* 306892SBrad.Beckmann@amd.com * The actual modelled switch. It use the perfect switch and a 316892SBrad.Beckmann@amd.com * Throttle object to control and bandwidth and timing *only for the 326892SBrad.Beckmann@amd.com * output port*. So here we have un-realistic modelling, since the 336892SBrad.Beckmann@amd.com * order of PerfectSwitch and Throttle objects get woke up affect the 346892SBrad.Beckmann@amd.com * message timing. A more accurate model would be having two set of 356892SBrad.Beckmann@amd.com * system states, one for this cycle, one for next cycle. And on the 366892SBrad.Beckmann@amd.com * cycle boundary swap the two set of states. 376892SBrad.Beckmann@amd.com */ 386892SBrad.Beckmann@amd.com 396892SBrad.Beckmann@amd.com#ifndef __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 406892SBrad.Beckmann@amd.com#define __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 416892SBrad.Beckmann@amd.com 426892SBrad.Beckmann@amd.com#include <iostream> 436892SBrad.Beckmann@amd.com#include <vector> 446892SBrad.Beckmann@amd.com 456892SBrad.Beckmann@amd.com#include "mem/ruby/common/Global.hh" 466892SBrad.Beckmann@amd.com 476892SBrad.Beckmann@amd.comclass MessageBuffer; 486892SBrad.Beckmann@amd.comclass PerfectSwitch; 496892SBrad.Beckmann@amd.comclass NetDest; 506892SBrad.Beckmann@amd.comclass SimpleNetwork; 516892SBrad.Beckmann@amd.comclass Throttle; 526893SBrad.Beckmann@amd.com 536892SBrad.Beckmann@amd.comclass Switch 546892SBrad.Beckmann@amd.com{ 556892SBrad.Beckmann@amd.com public: 566892SBrad.Beckmann@amd.com Switch(SwitchID sid, SimpleNetwork* network_ptr); 576893SBrad.Beckmann@amd.com ~Switch(); 586893SBrad.Beckmann@amd.com 596892SBrad.Beckmann@amd.com void addInPort(const std::vector<MessageBuffer*>& in); 606892SBrad.Beckmann@amd.com void addOutPort(const std::vector<MessageBuffer*>& out, 616892SBrad.Beckmann@amd.com const NetDest& routing_table_entry, int link_latency, 626892SBrad.Beckmann@amd.com int bw_multiplier); 636892SBrad.Beckmann@amd.com const Throttle* getThrottle(LinkID link_number) const; 646892SBrad.Beckmann@amd.com const std::vector<Throttle*>* getThrottles() const; 656892SBrad.Beckmann@amd.com void clearRoutingTables(); 666892SBrad.Beckmann@amd.com void clearBuffers(); 676892SBrad.Beckmann@amd.com void reconfigureOutPort(const NetDest& routing_table_entry); 686892SBrad.Beckmann@amd.com 696892SBrad.Beckmann@amd.com void printStats(std::ostream& out) const; 706892SBrad.Beckmann@amd.com void clearStats(); 716892SBrad.Beckmann@amd.com void printConfig(std::ostream& out) const; 726893SBrad.Beckmann@amd.com 736893SBrad.Beckmann@amd.com void print(std::ostream& out) const; 746892SBrad.Beckmann@amd.com 756892SBrad.Beckmann@amd.com private: 766892SBrad.Beckmann@amd.com // Private copy constructor and assignment operator 776892SBrad.Beckmann@amd.com Switch(const Switch& obj); 786892SBrad.Beckmann@amd.com Switch& operator=(const Switch& obj); 796892SBrad.Beckmann@amd.com 806892SBrad.Beckmann@amd.com PerfectSwitch* m_perfect_switch_ptr; 816892SBrad.Beckmann@amd.com SimpleNetwork* m_network_ptr; 826892SBrad.Beckmann@amd.com std::vector<Throttle*> m_throttles; 836892SBrad.Beckmann@amd.com std::vector<MessageBuffer*> m_buffers_to_free; 846892SBrad.Beckmann@amd.com SwitchID m_switch_id; 856892SBrad.Beckmann@amd.com}; 866892SBrad.Beckmann@amd.com 876892SBrad.Beckmann@amd.cominline std::ostream& 886893SBrad.Beckmann@amd.comoperator<<(std::ostream& out, const Switch& obj) 896893SBrad.Beckmann@amd.com{ 906893SBrad.Beckmann@amd.com obj.print(out); 916893SBrad.Beckmann@amd.com out << std::flush; 926893SBrad.Beckmann@amd.com return out; 936892SBrad.Beckmann@amd.com} 946892SBrad.Beckmann@amd.com 956892SBrad.Beckmann@amd.com#endif // __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 966892SBrad.Beckmann@amd.com