Switch.hh revision 7454:3a3e8e8cce1b
12623SN/A/* 27725SAli.Saidi@ARM.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 37725SAli.Saidi@ARM.com * All rights reserved. 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67725SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77725SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87725SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97725SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107725SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117725SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127725SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137725SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272623SN/A */ 282623SN/A 292623SN/A/* 302623SN/A * The actual modelled switch. It use the perfect switch and a 312623SN/A * Throttle object to control and bandwidth and timing *only for the 322623SN/A * output port*. So here we have un-realistic modelling, since the 332623SN/A * order of PerfectSwitch and Throttle objects get woke up affect the 342623SN/A * message timing. A more accurate model would be having two set of 352623SN/A * system states, one for this cycle, one for next cycle. And on the 362623SN/A * cycle boundary swap the two set of states. 372623SN/A */ 382623SN/A 392665Ssaidi@eecs.umich.edu#ifndef __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 402665Ssaidi@eecs.umich.edu#define __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 412623SN/A 422623SN/A#include <iostream> 433170Sstever@eecs.umich.edu#include <vector> 445103Ssaidi@eecs.umich.edu 452623SN/A#include "mem/ruby/common/Global.hh" 464040Ssaidi@eecs.umich.edu 476658Snate@binkert.orgclass MessageBuffer; 482623SN/Aclass PerfectSwitch; 492623SN/Aclass NetDest; 503348Sbinkertn@umich.educlass SimpleNetwork; 513348Sbinkertn@umich.educlass Throttle; 524762Snate@binkert.orgclass Network; 537678Sgblack@eecs.umich.edu 542901Ssaidi@eecs.umich.educlass Switch 552623SN/A{ 562623SN/A public: 572623SN/A Switch(SwitchID sid, SimpleNetwork* network_ptr); 582623SN/A ~Switch(); 592856Srdreslin@umich.edu 602856Srdreslin@umich.edu void addInPort(const std::vector<MessageBuffer*>& in); 612856Srdreslin@umich.edu void addOutPort(const std::vector<MessageBuffer*>& out, 622856Srdreslin@umich.edu const NetDest& routing_table_entry, int link_latency, 632856Srdreslin@umich.edu int bw_multiplier); 642856Srdreslin@umich.edu const Throttle* getThrottle(LinkID link_number) const; 652856Srdreslin@umich.edu const std::vector<Throttle*>* getThrottles() const; 662856Srdreslin@umich.edu void clearRoutingTables(); 672856Srdreslin@umich.edu void clearBuffers(); 682856Srdreslin@umich.edu void reconfigureOutPort(const NetDest& routing_table_entry); 692623SN/A 702623SN/A void printStats(std::ostream& out) const; 712623SN/A void clearStats(); 722623SN/A void printConfig(std::ostream& out) const; 732623SN/A 742623SN/A void print(std::ostream& out) const; 752680Sktlim@umich.edu 762680Sktlim@umich.edu private: 772623SN/A // Private copy constructor and assignment operator 782623SN/A Switch(const Switch& obj); 795712Shsul@eecs.umich.edu Switch& operator=(const Switch& obj); 802623SN/A 812623SN/A PerfectSwitch* m_perfect_switch_ptr; 822623SN/A Network* m_network_ptr; 832623SN/A std::vector<Throttle*> m_throttles; 842623SN/A std::vector<MessageBuffer*> m_buffers_to_free; 853349Sbinkertn@umich.edu SwitchID m_switch_id; 862623SN/A}; 872623SN/A 887823Ssteve.reinhardt@amd.cominline std::ostream& 892623SN/Aoperator<<(std::ostream& out, const Switch& obj) 902623SN/A{ 912623SN/A obj.print(out); 923349Sbinkertn@umich.edu out << std::flush; 932623SN/A return out; 943184Srdreslin@umich.edu} 953184Srdreslin@umich.edu 962623SN/A#endif // __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__ 972623SN/A