Switch.hh revision 6285:ce086eca1ede
12810Srdreslin@umich.edu 210343SCurtis.Dunham@arm.com/* 38702Sandreas.hansson@arm.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 48702Sandreas.hansson@arm.com * All rights reserved. 58702Sandreas.hansson@arm.com * 68702Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 78702Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 88702Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 98702Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 108702Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 118702Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 128702Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 138702Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 142810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 152810Srdreslin@umich.edu * this software without specific prior written permission. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282810Srdreslin@umich.edu */ 292810Srdreslin@umich.edu 302810Srdreslin@umich.edu/* 312810Srdreslin@umich.edu * $Id$ 322810Srdreslin@umich.edu * 332810Srdreslin@umich.edu * Description: The actual modelled switch. It use the perfect switch and a 342810Srdreslin@umich.edu * Throttle object to control and bandwidth and timing *only for 352810Srdreslin@umich.edu * the output port*. So here we have un-realistic modelling, 362810Srdreslin@umich.edu * since the order of PerfectSwitch and Throttle objects get 372810Srdreslin@umich.edu * woke up affect the message timing. A more accurate model would 382810Srdreslin@umich.edu * be having two set of system states, one for this cycle, one for 392810Srdreslin@umich.edu * next cycle. And on the cycle boundary swap the two set of 402810Srdreslin@umich.edu * states. 412810Srdreslin@umich.edu * 422810Srdreslin@umich.edu */ 434458Sstever@eecs.umich.edu 448856Sandreas.hansson@arm.com#ifndef Switch_H 452810Srdreslin@umich.edu#define Switch_H 462810Srdreslin@umich.edu 472810Srdreslin@umich.edu#include "mem/ruby/common/Global.hh" 482810Srdreslin@umich.edu#include "mem/gems_common/Vector.hh" 492810Srdreslin@umich.edu 502810Srdreslin@umich.educlass MessageBuffer; 512810Srdreslin@umich.educlass PerfectSwitch; 522810Srdreslin@umich.educlass NetDest; 532810Srdreslin@umich.educlass SimpleNetwork; 542810Srdreslin@umich.educlass Throttle; 552810Srdreslin@umich.educlass Network; 565338Sstever@gmail.com 575338Sstever@gmail.comclass Switch { 585338Sstever@gmail.compublic: 594458Sstever@eecs.umich.edu // Constructors 604458Sstever@eecs.umich.edu 612813Srdreslin@umich.edu // constructor specifying the number of ports 623861Sstever@eecs.umich.edu Switch(SwitchID sid, SimpleNetwork* network_ptr); 632810Srdreslin@umich.edu void addInPort(const Vector<MessageBuffer*>& in); 642810Srdreslin@umich.edu void addOutPort(const Vector<MessageBuffer*>& out, const NetDest& routing_table_entry, int link_latency, int bw_multiplier); 652810Srdreslin@umich.edu const Throttle* getThrottle(LinkID link_number) const; 662810Srdreslin@umich.edu const Vector<Throttle*>* getThrottles() const; 679264Sdjordje.kovacevic@arm.com void clearRoutingTables(); 682810Srdreslin@umich.edu void clearBuffers(); 694672Sstever@eecs.umich.edu void reconfigureOutPort(const NetDest& routing_table_entry); 702810Srdreslin@umich.edu 712810Srdreslin@umich.edu void printStats(ostream& out) const; 722810Srdreslin@umich.edu void clearStats(); 732810Srdreslin@umich.edu void printConfig(ostream& out) const; 742810Srdreslin@umich.edu 753860Sstever@eecs.umich.edu // Destructor 763860Sstever@eecs.umich.edu ~Switch(); 772810Srdreslin@umich.edu 782810Srdreslin@umich.edu void print(ostream& out) const; 799347SAndreas.Sandberg@arm.comprivate: 802810Srdreslin@umich.edu 818856Sandreas.hansson@arm.com // Private copy constructor and assignment operator 828856Sandreas.hansson@arm.com Switch(const Switch& obj); 838856Sandreas.hansson@arm.com Switch& operator=(const Switch& obj); 848856Sandreas.hansson@arm.com 858856Sandreas.hansson@arm.com // Data Members (m_ prefix) 863738Sstever@eecs.umich.edu PerfectSwitch* m_perfect_switch_ptr; 878856Sandreas.hansson@arm.com Network* m_network_ptr; 883738Sstever@eecs.umich.edu Vector<Throttle*> m_throttles; 898856Sandreas.hansson@arm.com Vector<MessageBuffer*> m_buffers_to_free; 908856Sandreas.hansson@arm.com SwitchID m_switch_id; 913738Sstever@eecs.umich.edu}; 928856Sandreas.hansson@arm.com 934478Sstever@eecs.umich.edu// Output operator declaration 948975Sandreas.hansson@arm.comostream& operator<<(ostream& out, const Switch& obj); 958948Sandreas.hansson@arm.com 968975Sandreas.hansson@arm.com// ******************* Definitions ******************* 973738Sstever@eecs.umich.edu 983738Sstever@eecs.umich.edu// Output operator definition 993738Sstever@eecs.umich.eduextern inline 1003738Sstever@eecs.umich.eduostream& operator<<(ostream& out, const Switch& obj) 1018856Sandreas.hansson@arm.com{ 1029090Sandreas.hansson@arm.com obj.print(out); 1038856Sandreas.hansson@arm.com out << flush; 1048856Sandreas.hansson@arm.com return out; 1058856Sandreas.hansson@arm.com} 1068856Sandreas.hansson@arm.com 1078856Sandreas.hansson@arm.com#endif //Switch_H 1088856Sandreas.hansson@arm.com