SimpleNetwork.hh revision 7054 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The SimpleNetwork class implements the interconnection
31 * SimpleNetwork between components (processor/cache components and
32 * memory/directory components).  The interconnection network as
33 * described here is not a physical network, but a programming concept
34 * used to implement all communication between components.  Thus parts
35 * of this 'network' may model the on-chip connections between cache
36 * controllers and directory controllers as well as the links between
37 * chip and network switches.
38 *
39 * Two conceptual networks, an address and data network, are modeled.
40 * The data network is unordered, where the address network provides
41 * and conforms to a global ordering of all transactions.
42 *
43 * Currently the data network is point-to-point and the address
44 * network is a broadcast network. These two distinct conceptual
45 * network can be modeled as physically separate networks or
46 * multiplexed over a single physical network.
47 *
48 * The network encapsulates all notion of virtual global time and is
49 * responsible for ordering the network transactions received.  This
50 * hides all of these ordering details from the processor/cache and
51 * directory/memory modules.
52 *
53 * FIXME: Various flavor of networks are provided as a compiler time
54 *        configurable. We currently include this SimpleNetwork in the
55 *        makefile's vpath, so that SimpleNetwork.cc can provide an alternative
56 *        version constructor for the abstract Network class. It is easy to
57 *        modify this to make network a runtime configuable. Just make the
58 *        abstract Network class take a enumeration parameter, and based on
59 *        that to initial proper network. Or even better, just make the ruby
60 *        system initializer choose the proper network to initiate.
61 */
62
63#ifndef __MEM_RUBY_NETWORK_SIMPLE_SIMPLENETWORK_HH__
64#define __MEM_RUBY_NETWORK_SIMPLE_SIMPLENETWORK_HH__
65
66#include "mem/gems_common/Vector.hh"
67#include "mem/ruby/common/Global.hh"
68#include "mem/ruby/network/Network.hh"
69#include "mem/ruby/system/NodeID.hh"
70#include "params/SimpleNetwork.hh"
71#include "sim/sim_object.hh"
72
73class NetDest;
74class MessageBuffer;
75class Throttle;
76class Switch;
77class Topology;
78
79class SimpleNetwork : public Network
80{
81  public:
82    typedef SimpleNetworkParams Params;
83    SimpleNetwork(const Params *p);
84    ~SimpleNetwork();
85
86    void init();
87
88    void printStats(ostream& out) const;
89    void clearStats();
90    void printConfig(ostream& out) const;
91
92    void reset();
93
94    // returns the queue requested for the given component
95    MessageBuffer* getToNetQueue(NodeID id, bool ordered, int network_num);
96    MessageBuffer* getFromNetQueue(NodeID id, bool ordered, int network_num);
97    virtual const Vector<Throttle*>* getThrottles(NodeID id) const;
98
99    bool isVNetOrdered(int vnet) { return m_ordered[vnet]; }
100    bool validVirtualNetwork(int vnet) { return m_in_use[vnet]; }
101
102    int getNumNodes() {return m_nodes; }
103
104    // Methods used by Topology to setup the network
105    void makeOutLink(SwitchID src, NodeID dest,
106        const NetDest& routing_table_entry, int link_latency, int link_weight,
107        int bw_multiplier, bool isReconfiguration);
108    void makeInLink(SwitchID src, NodeID dest,
109        const NetDest& routing_table_entry, int link_latency,
110        int bw_multiplier, bool isReconfiguration);
111    void makeInternalLink(SwitchID src, NodeID dest,
112        const NetDest& routing_table_entry, int link_latency, int link_weight,
113        int bw_multiplier, bool isReconfiguration);
114
115    void print(ostream& out) const;
116
117  private:
118    void checkNetworkAllocation(NodeID id, bool ordered, int network_num);
119    void addLink(SwitchID src, SwitchID dest, int link_latency);
120    void makeLink(SwitchID src, SwitchID dest,
121        const NetDest& routing_table_entry, int link_latency);
122    SwitchID createSwitch();
123    void makeTopology();
124    void linkTopology();
125
126    // Private copy constructor and assignment operator
127    SimpleNetwork(const SimpleNetwork& obj);
128    SimpleNetwork& operator=(const SimpleNetwork& obj);
129
130    // vector of queues from the components
131    Vector<Vector<MessageBuffer*> > m_toNetQueues;
132    Vector<Vector<MessageBuffer*> > m_fromNetQueues;
133
134    Vector<bool> m_in_use;
135    Vector<bool> m_ordered;
136    Vector<Switch*> m_switch_ptr_vector;
137    Vector<MessageBuffer*> m_buffers_to_free;
138    Vector<Switch*> m_endpoint_switches;
139};
140
141inline ostream&
142operator<<(ostream& out, const SimpleNetwork& obj)
143{
144    obj.print(out);
145    out << flush;
146    return out;
147}
148
149#endif // __MEM_RUBY_NETWORK_SIMPLE_SIMPLENETWORK_HH__
150