Topology.hh revision 6876
1 2/* 3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* 31 * Topology.hh 32 * 33 * Description: The topology here is configurable; it can be a hierachical 34 * (default one) or a 2D torus or a 2D torus with half switches 35 * killed. I think all input port has a 36 * one-input-one-output switch connected just to control and 37 * bandwidth, since we don't control bandwidth on input ports. 38 * Basically, the class has a vector of nodes and edges. First 39 * 2*m_nodes elements in the node vector are input and output 40 * ports. Edges are represented in two vectors of src and dest 41 * nodes. All edges have latency. 42 * 43 * $Id$ 44 * 45 * */ 46 47#ifndef TOPOLOGY_H 48#define TOPOLOGY_H 49 50#include "mem/ruby/common/Global.hh" 51#include "mem/gems_common/Vector.hh" 52#include "mem/ruby/system/NodeID.hh" 53#include "sim/sim_object.hh" 54#include "params/Topology.hh" 55 56class Network; 57class NetDest; 58 59typedef Vector < Vector <int> > Matrix; 60 61class Topology : public SimObject { 62public: 63 // Constructors 64 typedef TopologyParams Params; 65 Topology(const Params *p); 66 67 // Destructor 68 virtual ~Topology() {} 69 70 virtual void init(); 71 72 // Public Methods 73 void makeTopology(); 74 int numSwitches() const { return m_number_of_switches; } 75 void createLinks(bool isReconfiguration); 76 77 const string getName() { return m_name; } 78 void printStats(ostream& out) const {} 79 void clearStats() {} 80 void printConfig(ostream& out) const; 81 void print(ostream& out) const { out << "[Topology]"; } 82 83protected: 84 // Private Methods 85 SwitchID newSwitchID(); 86 void addLink(SwitchID src, SwitchID dest, int link_latency); 87 void addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier); 88 void addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier, int link_weight); 89 void makeLink(SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency, int weight, int bw_multiplier, bool isReconfiguration); 90 91 // void makeSwitchesPerChip(Vector< Vector < SwitchID > > &nodePairs, Vector<int> &latencies, Vector<int> &bw_multis, int numberOfChips); 92 93 string getDesignStr(); 94 // Private copy constructor and assignment operator 95 Topology(const Topology& obj); 96 Topology& operator=(const Topology& obj); 97 98 // Data Members (m_ prefix) 99 string m_name; 100 bool m_print_config; 101 Network* m_network_ptr; 102 string m_connections; 103 NodeID m_nodes; 104 int m_number_of_switches; 105 106 Vector<SwitchID> m_links_src_vector; 107 Vector<SwitchID> m_links_dest_vector; 108 Vector<int> m_links_latency_vector; 109 Vector<int> m_links_weight_vector; 110 Vector<int> m_bw_multiplier_vector; 111 112 Matrix m_component_latencies; 113 Matrix m_component_inter_switches; 114}; 115 116// Output operator declaration 117ostream& operator<<(ostream& out, const Topology& obj); 118 119// ******************* Definitions ******************* 120 121// Output operator definition 122extern inline 123ostream& operator<<(ostream& out, const Topology& obj) 124{ 125 obj.print(out); 126 out << flush; 127 return out; 128} 129 130#endif 131