Topology.hh revision 8257
16145SN/A/* 26145SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36145SN/A * All rights reserved. 46145SN/A * 56145SN/A * Redistribution and use in source and binary forms, with or without 66145SN/A * modification, are permitted provided that the following conditions are 76145SN/A * met: redistributions of source code must retain the above copyright 86145SN/A * notice, this list of conditions and the following disclaimer; 96145SN/A * redistributions in binary form must reproduce the above copyright 106145SN/A * notice, this list of conditions and the following disclaimer in the 116145SN/A * documentation and/or other materials provided with the distribution; 126145SN/A * neither the name of the copyright holders nor the names of its 136145SN/A * contributors may be used to endorse or promote products derived from 146145SN/A * this software without specific prior written permission. 156145SN/A * 166145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145SN/A */ 286145SN/A 296145SN/A/* 307054SN/A * The topology here is configurable; it can be a hierachical (default 317054SN/A * one) or a 2D torus or a 2D torus with half switches killed. I think 327054SN/A * all input port has a one-input-one-output switch connected just to 337054SN/A * control and bandwidth, since we don't control bandwidth on input 347054SN/A * ports. Basically, the class has a vector of nodes and edges. First 357054SN/A * 2*m_nodes elements in the node vector are input and output 367054SN/A * ports. Edges are represented in two vectors of src and dest 377054SN/A * nodes. All edges have latency. 387054SN/A */ 396145SN/A 407054SN/A#ifndef __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__ 417054SN/A#define __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__ 426145SN/A 437002SN/A#include <iostream> 447002SN/A#include <string> 457454SN/A#include <vector> 467002SN/A 478257SBrad.Beckmann@amd.com#include "mem/protocol/LinkDirection.hh" 486154SN/A#include "mem/ruby/common/Global.hh" 496154SN/A#include "mem/ruby/system/NodeID.hh" 507054SN/A#include "params/Topology.hh" 517054SN/A#include "sim/sim_object.hh" 526145SN/A 538257SBrad.Beckmann@amd.comclass NetDest; 546145SN/Aclass Network; 556145SN/A 567454SN/Atypedef std::vector<std::vector<int> > Matrix; 576145SN/A 588257SBrad.Beckmann@amd.comstruct LinkEntry 597054SN/A{ 608257SBrad.Beckmann@amd.com BasicLink *link; 618257SBrad.Beckmann@amd.com LinkDirection direction; 626879SN/A}; 636879SN/A 648257SBrad.Beckmann@amd.comtypedef std::map<std::pair<int, int>, LinkEntry> LinkMap; 656879SN/A 667054SN/Aclass Topology : public SimObject 677054SN/A{ 687054SN/A public: 696876SN/A typedef TopologyParams Params; 706876SN/A Topology(const Params *p); 717054SN/A virtual ~Topology() {} 726879SN/A const Params *params() const { return (const Params *)_params; } 736145SN/A 748257SBrad.Beckmann@amd.com void init(); 757054SN/A int numSwitches() const { return m_number_of_switches; } 767054SN/A void createLinks(Network *net, bool isReconfiguration); 776285SN/A 787054SN/A void initNetworkPtr(Network* net_ptr); 796145SN/A 807054SN/A const std::string getName() { return m_name; } 817054SN/A void printStats(std::ostream& out) const; 827054SN/A void clearStats(); 837054SN/A void printConfig(std::ostream& out) const; 847054SN/A void print(std::ostream& out) const { out << "[Topology]"; } 856881SN/A 867054SN/A protected: 878257SBrad.Beckmann@amd.com void addLink(SwitchID src, SwitchID dest, BasicLink* link, 888257SBrad.Beckmann@amd.com LinkDirection dir); 897054SN/A void makeLink(Network *net, SwitchID src, SwitchID dest, 908257SBrad.Beckmann@amd.com const NetDest& routing_table_entry, 918257SBrad.Beckmann@amd.com bool isReconfiguration); 926145SN/A 937054SN/A std::string getDesignStr(); 947054SN/A // Private copy constructor and assignment operator 957054SN/A Topology(const Topology& obj); 967054SN/A Topology& operator=(const Topology& obj); 976145SN/A 987054SN/A std::string m_name; 997054SN/A bool m_print_config; 1007054SN/A NodeID m_nodes; 1017054SN/A int m_number_of_switches; 1026145SN/A 1037454SN/A std::vector<AbstractController*> m_controller_vector; 1048257SBrad.Beckmann@amd.com std::vector<BasicExtLink*> m_ext_link_vector; 1058257SBrad.Beckmann@amd.com std::vector<BasicIntLink*> m_int_link_vector; 1066881SN/A 1077054SN/A Matrix m_component_latencies; 1087054SN/A Matrix m_component_inter_switches; 1098257SBrad.Beckmann@amd.com 1108257SBrad.Beckmann@amd.com LinkMap m_link_map; 1118257SBrad.Beckmann@amd.com std::vector<BasicRouter*> m_router_vector; 1126145SN/A}; 1136145SN/A 1147054SN/Ainline std::ostream& 1157054SN/Aoperator<<(std::ostream& out, const Topology& obj) 1166145SN/A{ 1177054SN/A obj.print(out); 1187054SN/A out << std::flush; 1197054SN/A return out; 1206145SN/A} 1216145SN/A 1227054SN/A#endif // __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__ 123