Topology.hh revision 11096
16145SN/A/* 26145SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36145SN/A * All rights reserved. 46145SN/A * 56145SN/A * Redistribution and use in source and binary forms, with or without 66145SN/A * modification, are permitted provided that the following conditions are 76145SN/A * met: redistributions of source code must retain the above copyright 86145SN/A * notice, this list of conditions and the following disclaimer; 96145SN/A * redistributions in binary form must reproduce the above copyright 106145SN/A * notice, this list of conditions and the following disclaimer in the 116145SN/A * documentation and/or other materials provided with the distribution; 126145SN/A * neither the name of the copyright holders nor the names of its 136145SN/A * contributors may be used to endorse or promote products derived from 146145SN/A * this software without specific prior written permission. 156145SN/A * 166145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145SN/A */ 286145SN/A 296145SN/A/* 307054SN/A * The topology here is configurable; it can be a hierachical (default 317054SN/A * one) or a 2D torus or a 2D torus with half switches killed. I think 327054SN/A * all input port has a one-input-one-output switch connected just to 337054SN/A * control and bandwidth, since we don't control bandwidth on input 347054SN/A * ports. Basically, the class has a vector of nodes and edges. First 357054SN/A * 2*m_nodes elements in the node vector are input and output 367054SN/A * ports. Edges are represented in two vectors of src and dest 377054SN/A * nodes. All edges have latency. 387054SN/A */ 396145SN/A 409594Snilay@cs.wisc.edu#ifndef __MEM_RUBY_NETWORK_TOPOLOGY_HH__ 419594Snilay@cs.wisc.edu#define __MEM_RUBY_NETWORK_TOPOLOGY_HH__ 426145SN/A 437002SN/A#include <iostream> 447002SN/A#include <string> 457454SN/A#include <vector> 467002SN/A 478257SBrad.Beckmann@amd.com#include "mem/protocol/LinkDirection.hh" 488608Snilay@cs.wisc.edu#include "mem/ruby/common/TypeDefines.hh" 499594Snilay@cs.wisc.edu#include "mem/ruby/network/BasicLink.hh" 506145SN/A 518257SBrad.Beckmann@amd.comclass NetDest; 526145SN/Aclass Network; 536145SN/A 547454SN/Atypedef std::vector<std::vector<int> > Matrix; 556145SN/A 568257SBrad.Beckmann@amd.comstruct LinkEntry 577054SN/A{ 588257SBrad.Beckmann@amd.com BasicLink *link; 598257SBrad.Beckmann@amd.com LinkDirection direction; 606879SN/A}; 616879SN/A 6210005Snilay@cs.wisc.edutypedef std::map<std::pair<SwitchID, SwitchID>, LinkEntry> LinkMap; 636879SN/A 649594Snilay@cs.wisc.educlass Topology 657054SN/A{ 667054SN/A public: 6711096Snilay@cs.wisc.edu Topology(uint32_t num_routers, const std::vector<BasicExtLink *> &ext_links, 6811096Snilay@cs.wisc.edu const std::vector<BasicIntLink *> &int_links); 696145SN/A 709594Snilay@cs.wisc.edu uint32_t numSwitches() const { return m_number_of_switches; } 719799Snilay@cs.wisc.edu void createLinks(Network *net); 727054SN/A void print(std::ostream& out) const { out << "[Topology]"; } 736881SN/A 7411096Snilay@cs.wisc.edu private: 758257SBrad.Beckmann@amd.com void addLink(SwitchID src, SwitchID dest, BasicLink* link, 768257SBrad.Beckmann@amd.com LinkDirection dir); 777054SN/A void makeLink(Network *net, SwitchID src, SwitchID dest, 789799Snilay@cs.wisc.edu const NetDest& routing_table_entry); 796145SN/A 8011096Snilay@cs.wisc.edu // Helper functions based on chapter 29 of Cormen et al. 8111096Snilay@cs.wisc.edu void extend_shortest_path(Matrix ¤t_dist, Matrix &latencies, 8211096Snilay@cs.wisc.edu Matrix &inter_switches); 8311096Snilay@cs.wisc.edu 8411096Snilay@cs.wisc.edu std::vector<std::vector<int>> shortest_path(const Matrix &weights, 8511096Snilay@cs.wisc.edu Matrix &latencies, Matrix &inter_switches); 8611096Snilay@cs.wisc.edu 8711096Snilay@cs.wisc.edu bool link_is_shortest_path_to_node(SwitchID src, SwitchID next, 8811096Snilay@cs.wisc.edu SwitchID final, const Matrix &weights, const Matrix &dist); 8911096Snilay@cs.wisc.edu 9011096Snilay@cs.wisc.edu NetDest shortest_path_to_node(SwitchID src, SwitchID next, 9111096Snilay@cs.wisc.edu const Matrix &weights, const Matrix &dist); 9211096Snilay@cs.wisc.edu 9311096Snilay@cs.wisc.edu const uint32_t m_nodes; 9411096Snilay@cs.wisc.edu const uint32_t m_number_of_switches; 956145SN/A 968257SBrad.Beckmann@amd.com std::vector<BasicExtLink*> m_ext_link_vector; 978257SBrad.Beckmann@amd.com std::vector<BasicIntLink*> m_int_link_vector; 986881SN/A 998257SBrad.Beckmann@amd.com LinkMap m_link_map; 1006145SN/A}; 1016145SN/A 1027054SN/Ainline std::ostream& 1037054SN/Aoperator<<(std::ostream& out, const Topology& obj) 1046145SN/A{ 1057054SN/A obj.print(out); 1067054SN/A out << std::flush; 1077054SN/A return out; 1086145SN/A} 1096145SN/A 1109594Snilay@cs.wisc.edu#endif // __MEM_RUBY_NETWORK_TOPOLOGY_HH__ 111