Topology.cc revision 13661
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "mem/ruby/network/Topology.hh" 30 31#include <cassert> 32 33#include "base/trace.hh" 34#include "debug/RubyNetwork.hh" 35#include "mem/ruby/common/NetDest.hh" 36#include "mem/ruby/network/BasicLink.hh" 37#include "mem/ruby/network/Network.hh" 38#include "mem/ruby/slicc_interface/AbstractController.hh" 39 40using namespace std; 41 42const int INFINITE_LATENCY = 10000; // Yes, this is a big hack 43 44// Note: In this file, we use the first 2*m_nodes SwitchIDs to 45// represent the input and output endpoint links. These really are 46// not 'switches', as they will not have a Switch object allocated for 47// them. The first m_nodes SwitchIDs are the links into the network, 48// the second m_nodes set of SwitchIDs represent the the output queues 49// of the network. 50 51Topology::Topology(uint32_t num_routers, 52 const vector<BasicExtLink *> &ext_links, 53 const vector<BasicIntLink *> &int_links) 54 : m_nodes(MachineType_base_number(MachineType_NUM)), 55 m_number_of_switches(num_routers), 56 m_ext_link_vector(ext_links), m_int_link_vector(int_links) 57{ 58 // Total nodes/controllers in network 59 assert(m_nodes > 1); 60 61 // analyze both the internal and external links, create data structures. 62 // The python created external links are bi-directional, 63 // and the python created internal links are uni-directional. 64 // The networks and topology utilize uni-directional links. 65 // Thus each external link is converted to two calls to addLink, 66 // one for each direction. 67 // 68 // External Links 69 for (vector<BasicExtLink*>::const_iterator i = ext_links.begin(); 70 i != ext_links.end(); ++i) { 71 BasicExtLink *ext_link = (*i); 72 AbstractController *abs_cntrl = ext_link->params()->ext_node; 73 BasicRouter *router = ext_link->params()->int_node; 74 75 int machine_base_idx = MachineType_base_number(abs_cntrl->getType()); 76 int ext_idx1 = machine_base_idx + abs_cntrl->getVersion(); 77 int ext_idx2 = ext_idx1 + m_nodes; 78 int int_idx = router->params()->router_id + 2*m_nodes; 79 80 // create the internal uni-directional links in both directions 81 // ext to int 82 addLink(ext_idx1, int_idx, ext_link); 83 // int to ext 84 addLink(int_idx, ext_idx2, ext_link); 85 } 86 87 // Internal Links 88 for (vector<BasicIntLink*>::const_iterator i = int_links.begin(); 89 i != int_links.end(); ++i) { 90 BasicIntLink *int_link = (*i); 91 BasicRouter *router_src = int_link->params()->src_node; 92 BasicRouter *router_dst = int_link->params()->dst_node; 93 94 PortDirection src_outport = int_link->params()->src_outport; 95 PortDirection dst_inport = int_link->params()->dst_inport; 96 97 // Store the IntLink pointers for later 98 m_int_link_vector.push_back(int_link); 99 100 int src = router_src->params()->router_id + 2*m_nodes; 101 int dst = router_dst->params()->router_id + 2*m_nodes; 102 103 // create the internal uni-directional link from src to dst 104 addLink(src, dst, int_link, src_outport, dst_inport); 105 } 106} 107 108void 109Topology::createLinks(Network *net) 110{ 111 // Find maximum switchID 112 SwitchID max_switch_id = 0; 113 for (LinkMap::const_iterator i = m_link_map.begin(); 114 i != m_link_map.end(); ++i) { 115 std::pair<SwitchID, SwitchID> src_dest = (*i).first; 116 max_switch_id = max(max_switch_id, src_dest.first); 117 max_switch_id = max(max_switch_id, src_dest.second); 118 } 119 120 // Initialize weight, latency, and inter switched vectors 121 int num_switches = max_switch_id+1; 122 Matrix topology_weights(num_switches, 123 vector<int>(num_switches, INFINITE_LATENCY)); 124 Matrix component_latencies(num_switches, 125 vector<int>(num_switches, -1)); 126 Matrix component_inter_switches(num_switches, 127 vector<int>(num_switches, 0)); 128 129 // Set identity weights to zero 130 for (int i = 0; i < topology_weights.size(); i++) { 131 topology_weights[i][i] = 0; 132 } 133 134 // Fill in the topology weights and bandwidth multipliers 135 for (LinkMap::const_iterator i = m_link_map.begin(); 136 i != m_link_map.end(); ++i) { 137 std::pair<int, int> src_dest = (*i).first; 138 BasicLink* link = (*i).second.link; 139 int src = src_dest.first; 140 int dst = src_dest.second; 141 component_latencies[src][dst] = link->m_latency; 142 topology_weights[src][dst] = link->m_weight; 143 } 144 145 // Walk topology and hookup the links 146 Matrix dist = shortest_path(topology_weights, component_latencies, 147 component_inter_switches); 148 149 for (int i = 0; i < topology_weights.size(); i++) { 150 for (int j = 0; j < topology_weights[i].size(); j++) { 151 int weight = topology_weights[i][j]; 152 if (weight > 0 && weight != INFINITE_LATENCY) { 153 NetDest destination_set = 154 shortest_path_to_node(i, j, topology_weights, dist); 155 makeLink(net, i, j, destination_set); 156 } 157 } 158 } 159} 160 161void 162Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link, 163 PortDirection src_outport_dirn, 164 PortDirection dst_inport_dirn) 165{ 166 assert(src <= m_number_of_switches+m_nodes+m_nodes); 167 assert(dest <= m_number_of_switches+m_nodes+m_nodes); 168 169 std::pair<int, int> src_dest_pair; 170 LinkEntry link_entry; 171 172 src_dest_pair.first = src; 173 src_dest_pair.second = dest; 174 link_entry.link = link; 175 link_entry.src_outport_dirn = src_outport_dirn; 176 link_entry.dst_inport_dirn = dst_inport_dirn; 177 m_link_map[src_dest_pair] = link_entry; 178} 179 180void 181Topology::makeLink(Network *net, SwitchID src, SwitchID dest, 182 const NetDest& routing_table_entry) 183{ 184 // Make sure we're not trying to connect two end-point nodes 185 // directly together 186 assert(src >= 2 * m_nodes || dest >= 2 * m_nodes); 187 188 std::pair<int, int> src_dest; 189 LinkEntry link_entry; 190 191 if (src < m_nodes) { 192 src_dest.first = src; 193 src_dest.second = dest; 194 link_entry = m_link_map[src_dest]; 195 net->makeExtInLink(src, dest - (2 * m_nodes), link_entry.link, 196 routing_table_entry); 197 } else if (dest < 2*m_nodes) { 198 assert(dest >= m_nodes); 199 NodeID node = dest - m_nodes; 200 src_dest.first = src; 201 src_dest.second = dest; 202 link_entry = m_link_map[src_dest]; 203 net->makeExtOutLink(src - (2 * m_nodes), node, link_entry.link, 204 routing_table_entry); 205 } else { 206 assert((src >= 2 * m_nodes) && (dest >= 2 * m_nodes)); 207 src_dest.first = src; 208 src_dest.second = dest; 209 link_entry = m_link_map[src_dest]; 210 net->makeInternalLink(src - (2 * m_nodes), dest - (2 * m_nodes), 211 link_entry.link, 212 routing_table_entry, 213 link_entry.src_outport_dirn, 214 link_entry.dst_inport_dirn); 215 } 216} 217 218// The following all-pairs shortest path algorithm is based on the 219// discussion from Cormen et al., Chapter 26.1. 220void 221Topology::extend_shortest_path(Matrix ¤t_dist, Matrix &latencies, 222 Matrix &inter_switches) 223{ 224 bool change = true; 225 int nodes = current_dist.size(); 226 227 while (change) { 228 change = false; 229 for (int i = 0; i < nodes; i++) { 230 for (int j = 0; j < nodes; j++) { 231 int minimum = current_dist[i][j]; 232 int previous_minimum = minimum; 233 int intermediate_switch = -1; 234 for (int k = 0; k < nodes; k++) { 235 minimum = min(minimum, 236 current_dist[i][k] + current_dist[k][j]); 237 if (previous_minimum != minimum) { 238 intermediate_switch = k; 239 inter_switches[i][j] = 240 inter_switches[i][k] + 241 inter_switches[k][j] + 1; 242 } 243 previous_minimum = minimum; 244 } 245 if (current_dist[i][j] != minimum) { 246 change = true; 247 current_dist[i][j] = minimum; 248 assert(intermediate_switch >= 0); 249 assert(intermediate_switch < latencies[i].size()); 250 latencies[i][j] = latencies[i][intermediate_switch] + 251 latencies[intermediate_switch][j]; 252 } 253 } 254 } 255 } 256} 257 258Matrix 259Topology::shortest_path(const Matrix &weights, Matrix &latencies, 260 Matrix &inter_switches) 261{ 262 Matrix dist = weights; 263 extend_shortest_path(dist, latencies, inter_switches); 264 return dist; 265} 266 267bool 268Topology::link_is_shortest_path_to_node(SwitchID src, SwitchID next, 269 SwitchID final, const Matrix &weights, 270 const Matrix &dist) 271{ 272 return weights[src][next] + dist[next][final] == dist[src][final]; 273} 274 275NetDest 276Topology::shortest_path_to_node(SwitchID src, SwitchID next, 277 const Matrix &weights, const Matrix &dist) 278{ 279 NetDest result; 280 int d = 0; 281 int machines; 282 int max_machines; 283 284 machines = MachineType_NUM; 285 max_machines = MachineType_base_number(MachineType_NUM); 286 287 for (int m = 0; m < machines; m++) { 288 for (NodeID i = 0; i < MachineType_base_count((MachineType)m); i++) { 289 // we use "d+max_machines" below since the "destination" 290 // switches for the machines are numbered 291 // [MachineType_base_number(MachineType_NUM)... 292 // 2*MachineType_base_number(MachineType_NUM)-1] for the 293 // component network 294 if (link_is_shortest_path_to_node(src, next, d + max_machines, 295 weights, dist)) { 296 MachineID mach = {(MachineType)m, i}; 297 result.add(mach); 298 } 299 d++; 300 } 301 } 302 303 DPRINTF(RubyNetwork, "Returning shortest path\n" 304 "(src-(2*max_machines)): %d, (next-(2*max_machines)): %d, " 305 "src: %d, next: %d, result: %s\n", 306 (src-(2*max_machines)), (next-(2*max_machines)), 307 src, next, result); 308 309 return result; 310} 311