Topology.cc revision 8257
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cassert>
30
31#include "debug/RubyNetwork.hh"
32#include "mem/protocol/MachineType.hh"
33#include "mem/protocol/Protocol.hh"
34#include "mem/protocol/TopologyType.hh"
35#include "mem/ruby/common/NetDest.hh"
36#include "mem/ruby/network/BasicLink.hh"
37#include "mem/ruby/network/BasicRouter.hh"
38#include "mem/ruby/network/Network.hh"
39#include "mem/ruby/network/Topology.hh"
40#include "mem/ruby/slicc_interface/AbstractController.hh"
41#include "mem/ruby/system/System.hh"
42
43using namespace std;
44
45const int INFINITE_LATENCY = 10000; // Yes, this is a big hack
46
47class BasicRouter;
48
49// Note: In this file, we use the first 2*m_nodes SwitchIDs to
50// represent the input and output endpoint links.  These really are
51// not 'switches', as they will not have a Switch object allocated for
52// them. The first m_nodes SwitchIDs are the links into the network,
53// the second m_nodes set of SwitchIDs represent the the output queues
54// of the network.
55
56// Helper functions based on chapter 29 of Cormen et al.
57void extend_shortest_path(Matrix& current_dist, Matrix& latencies,
58    Matrix& inter_switches);
59Matrix shortest_path(const Matrix& weights, Matrix& latencies,
60    Matrix& inter_switches);
61bool link_is_shortest_path_to_node(SwitchID src, SwitchID next,
62    SwitchID final, const Matrix& weights, const Matrix& dist);
63NetDest shortest_path_to_node(SwitchID src, SwitchID next,
64    const Matrix& weights, const Matrix& dist);
65
66Topology::Topology(const Params *p)
67    : SimObject(p)
68{
69    m_print_config = p->print_config;
70    m_number_of_switches = p->routers.size();
71
72    // initialize component latencies record
73    m_component_latencies.resize(0);
74    m_component_inter_switches.resize(0);
75
76    // Total nodes/controllers in network
77    // Must make sure this is called after the State Machine constructors
78    m_nodes = MachineType_base_number(MachineType_NUM);
79    assert(m_nodes > 1);
80
81    if (m_nodes != params()->ext_links.size() &&
82        m_nodes != params()->ext_links.size()) {
83        fatal("m_nodes (%d) != ext_links vector length (%d)\n",
84              m_nodes != params()->ext_links.size());
85    }
86
87    // analyze both the internal and external links, create data structures
88    // Note that the python created links are bi-directional, but that the
89    // topology and networks utilize uni-directional links.  Thus each
90    // BasicLink is converted to two calls to add link, on for each direction
91    for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin();
92         i != params()->ext_links.end(); ++i) {
93        BasicExtLink *ext_link = (*i);
94        AbstractController *abs_cntrl = ext_link->params()->ext_node;
95        BasicRouter *router = ext_link->params()->int_node;
96
97        // Store the controller and ExtLink pointers for later
98        m_controller_vector.push_back(abs_cntrl);
99        m_ext_link_vector.push_back(ext_link);
100
101        int ext_idx1 = abs_cntrl->params()->cntrl_id;
102        int ext_idx2 = ext_idx1 + m_nodes;
103        int int_idx = router->params()->router_id + 2*m_nodes;
104
105        // create the internal uni-directional links in both directions
106        //   the first direction is marked: In
107        addLink(ext_idx1, int_idx, ext_link, LinkDirection_In);
108        //   the first direction is marked: Out
109        addLink(int_idx, ext_idx2, ext_link, LinkDirection_Out);
110    }
111
112    for (vector<BasicIntLink*>::const_iterator i = params()->int_links.begin();
113         i != params()->int_links.end(); ++i) {
114        BasicIntLink *int_link = (*i);
115        BasicRouter *router_a = int_link->params()->node_a;
116        BasicRouter *router_b = int_link->params()->node_b;
117
118        // Store the IntLink pointers for later
119        m_int_link_vector.push_back(int_link);
120
121        int a = router_a->params()->router_id + 2*m_nodes;
122        int b = router_b->params()->router_id + 2*m_nodes;
123
124        // create the internal uni-directional links in both directions
125        //   the first direction is marked: In
126        addLink(a, b, int_link, LinkDirection_In);
127        //   the second direction is marked: Out
128        addLink(b, a, int_link, LinkDirection_Out);
129    }
130}
131
132void
133Topology::init()
134{
135}
136
137
138void
139Topology::initNetworkPtr(Network* net_ptr)
140{
141    for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin();
142         i != params()->ext_links.end(); ++i) {
143        BasicExtLink *ext_link = (*i);
144        AbstractController *abs_cntrl = ext_link->params()->ext_node;
145        abs_cntrl->initNetworkPtr(net_ptr);
146    }
147}
148
149void
150Topology::createLinks(Network *net, bool isReconfiguration)
151{
152    // Find maximum switchID
153    SwitchID max_switch_id = 0;
154    for (LinkMap::const_iterator i = m_link_map.begin();
155         i != m_link_map.end(); ++i) {
156        std::pair<int, int> src_dest = (*i).first;
157        max_switch_id = max(max_switch_id, src_dest.first);
158        max_switch_id = max(max_switch_id, src_dest.second);
159    }
160
161    // Initialize weight, latency, and inter switched vectors
162    Matrix topology_weights;
163    int num_switches = max_switch_id+1;
164    topology_weights.resize(num_switches);
165    m_component_latencies.resize(num_switches);
166    m_component_inter_switches.resize(num_switches);
167
168    for (int i = 0; i < topology_weights.size(); i++) {
169        topology_weights[i].resize(num_switches);
170        m_component_latencies[i].resize(num_switches);
171        m_component_inter_switches[i].resize(num_switches);
172
173        for (int j = 0; j < topology_weights[i].size(); j++) {
174            topology_weights[i][j] = INFINITE_LATENCY;
175
176            // initialize to invalid values
177            m_component_latencies[i][j] = -1;
178
179            // initially assume direct connections / no intermediate
180            // switches between components
181            m_component_inter_switches[i][j] = 0;
182        }
183    }
184
185    // Set identity weights to zero
186    for (int i = 0; i < topology_weights.size(); i++) {
187        topology_weights[i][i] = 0;
188    }
189
190    // Fill in the topology weights and bandwidth multipliers
191    for (LinkMap::const_iterator i = m_link_map.begin();
192         i != m_link_map.end(); ++i) {
193        std::pair<int, int> src_dest = (*i).first;
194        BasicLink* link = (*i).second.link;
195        int src = src_dest.first;
196        int dst = src_dest.second;
197        m_component_latencies[src][dst] = link->m_latency;
198        topology_weights[src][dst] = link->m_weight;
199    }
200
201    // Walk topology and hookup the links
202    Matrix dist = shortest_path(topology_weights, m_component_latencies,
203        m_component_inter_switches);
204    for (int i = 0; i < topology_weights.size(); i++) {
205        for (int j = 0; j < topology_weights[i].size(); j++) {
206            int weight = topology_weights[i][j];
207            if (weight > 0 && weight != INFINITE_LATENCY) {
208                NetDest destination_set = shortest_path_to_node(i, j,
209                                                     topology_weights, dist);
210                makeLink(net, i, j, destination_set, isReconfiguration);
211            }
212        }
213    }
214}
215
216void
217Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link,
218                  LinkDirection dir)
219{
220    assert(src <= m_number_of_switches+m_nodes+m_nodes);
221    assert(dest <= m_number_of_switches+m_nodes+m_nodes);
222
223    std::pair<int, int> src_dest_pair;
224    LinkEntry link_entry;
225
226    src_dest_pair.first = src;
227    src_dest_pair.second = dest;
228    link_entry.direction = dir;
229    link_entry.link = link;
230    m_link_map[src_dest_pair] = link_entry;
231}
232
233void
234Topology::makeLink(Network *net, SwitchID src, SwitchID dest,
235                   const NetDest& routing_table_entry, bool isReconfiguration)
236{
237    // Make sure we're not trying to connect two end-point nodes
238    // directly together
239    assert(src >= 2 * m_nodes || dest >= 2 * m_nodes);
240
241    std::pair<int, int> src_dest;
242    LinkEntry link_entry;
243
244    if (src < m_nodes) {
245        src_dest.first = src;
246        src_dest.second = dest;
247        link_entry = m_link_map[src_dest];
248        net->makeInLink(src, dest - (2 * m_nodes), link_entry.link,
249                        link_entry.direction,
250                        routing_table_entry,
251                        isReconfiguration);
252    } else if (dest < 2*m_nodes) {
253        assert(dest >= m_nodes);
254        NodeID node = dest - m_nodes;
255        src_dest.first = src;
256        src_dest.second = dest;
257        link_entry = m_link_map[src_dest];
258        net->makeOutLink(src - (2 * m_nodes), node, link_entry.link,
259                         link_entry.direction,
260                         routing_table_entry,
261                         isReconfiguration);
262    } else {
263        assert((src >= 2 * m_nodes) && (dest >= 2 * m_nodes));
264        src_dest.first = src;
265        src_dest.second = dest;
266        link_entry = m_link_map[src_dest];
267        net->makeInternalLink(src - (2 * m_nodes), dest - (2 * m_nodes),
268                              link_entry.link, link_entry.direction,
269                              routing_table_entry, isReconfiguration);
270    }
271}
272
273void
274Topology::printStats(std::ostream& out) const
275{
276    for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) {
277        m_controller_vector[cntrl]->printStats(out);
278    }
279}
280
281void
282Topology::clearStats()
283{
284    for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) {
285        m_controller_vector[cntrl]->clearStats();
286    }
287}
288
289void
290Topology::printConfig(std::ostream& out) const
291{
292    if (m_print_config == false)
293        return;
294
295    assert(m_component_latencies.size() > 0);
296
297    out << "--- Begin Topology Print ---" << endl
298        << endl
299        << "Topology print ONLY indicates the _NETWORK_ latency between two "
300        << "machines" << endl
301        << "It does NOT include the latency within the machines" << endl
302        << endl;
303
304    for (int m = 0; m < MachineType_NUM; m++) {
305        int i_end = MachineType_base_count((MachineType)m);
306        for (int i = 0; i < i_end; i++) {
307            MachineID cur_mach = {(MachineType)m, i};
308            out << cur_mach << " Network Latencies" << endl;
309            for (int n = 0; n < MachineType_NUM; n++) {
310                int j_end = MachineType_base_count((MachineType)n);
311                for (int j = 0; j < j_end; j++) {
312                    MachineID dest_mach = {(MachineType)n, j};
313                    if (cur_mach == dest_mach)
314                        continue;
315
316                    int src = MachineType_base_number((MachineType)m) + i;
317                    int dst = MachineType_base_number(MachineType_NUM) +
318                        MachineType_base_number((MachineType)n) + j;
319                    int link_latency = m_component_latencies[src][dst];
320                    int intermediate_switches =
321                        m_component_inter_switches[src][dst];
322
323                    // NOTE switches are assumed to have single
324                    // cycle latency
325                    out << "  " << cur_mach << " -> " << dest_mach
326                        << " net_lat: "
327                        << link_latency + intermediate_switches << endl;
328                }
329            }
330            out << endl;
331        }
332    }
333
334    out << "--- End Topology Print ---" << endl;
335}
336
337// The following all-pairs shortest path algorithm is based on the
338// discussion from Cormen et al., Chapter 26.1.
339void
340extend_shortest_path(Matrix& current_dist, Matrix& latencies,
341    Matrix& inter_switches)
342{
343    bool change = true;
344    int nodes = current_dist.size();
345
346    while (change) {
347        change = false;
348        for (int i = 0; i < nodes; i++) {
349            for (int j = 0; j < nodes; j++) {
350                int minimum = current_dist[i][j];
351                int previous_minimum = minimum;
352                int intermediate_switch = -1;
353                for (int k = 0; k < nodes; k++) {
354                    minimum = min(minimum,
355                        current_dist[i][k] + current_dist[k][j]);
356                    if (previous_minimum != minimum) {
357                        intermediate_switch = k;
358                        inter_switches[i][j] =
359                            inter_switches[i][k] +
360                            inter_switches[k][j] + 1;
361                    }
362                    previous_minimum = minimum;
363                }
364                if (current_dist[i][j] != minimum) {
365                    change = true;
366                    current_dist[i][j] = minimum;
367                    assert(intermediate_switch >= 0);
368                    assert(intermediate_switch < latencies[i].size());
369                    latencies[i][j] = latencies[i][intermediate_switch] +
370                        latencies[intermediate_switch][j];
371                }
372            }
373        }
374    }
375}
376
377Matrix
378shortest_path(const Matrix& weights, Matrix& latencies, Matrix& inter_switches)
379{
380    Matrix dist = weights;
381    extend_shortest_path(dist, latencies, inter_switches);
382    return dist;
383}
384
385bool
386link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final,
387    const Matrix& weights, const Matrix& dist)
388{
389    return weights[src][next] + dist[next][final] == dist[src][final];
390}
391
392NetDest
393shortest_path_to_node(SwitchID src, SwitchID next, const Matrix& weights,
394    const Matrix& dist)
395{
396    NetDest result;
397    int d = 0;
398    int machines;
399    int max_machines;
400
401    machines = MachineType_NUM;
402    max_machines = MachineType_base_number(MachineType_NUM);
403
404    for (int m = 0; m < machines; m++) {
405        for (int i = 0; i < MachineType_base_count((MachineType)m); i++) {
406            // we use "d+max_machines" below since the "destination"
407            // switches for the machines are numbered
408            // [MachineType_base_number(MachineType_NUM)...
409            //  2*MachineType_base_number(MachineType_NUM)-1] for the
410            // component network
411            if (link_is_shortest_path_to_node(src, next, d + max_machines,
412                    weights, dist)) {
413                MachineID mach = {(MachineType)m, i};
414                result.add(mach);
415            }
416            d++;
417        }
418    }
419
420    DPRINTF(RubyNetwork, "Returning shortest path\n"
421            "(src-(2*max_machines)): %d, (next-(2*max_machines)): %d, "
422            "src: %d, next: %d, result: %s\n",
423            (src-(2*max_machines)), (next-(2*max_machines)),
424            src, next, result);
425
426    return result;
427}
428
429Topology *
430TopologyParams::create()
431{
432    return new Topology(this);
433}
434
435