Topology.cc revision 7832
12810SN/A/* 211375Sandreas.hansson@arm.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * Redistribution and use in source and binary forms, with or without 69347SAndreas.Sandberg@arm.com * modification, are permitted provided that the following conditions are 79347SAndreas.Sandberg@arm.com * met: redistributions of source code must retain the above copyright 89347SAndreas.Sandberg@arm.com * notice, this list of conditions and the following disclaimer; 99347SAndreas.Sandberg@arm.com * redistributions in binary form must reproduce the above copyright 109347SAndreas.Sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 119347SAndreas.Sandberg@arm.com * documentation and/or other materials provided with the distribution; 129347SAndreas.Sandberg@arm.com * neither the name of the copyright holders nor the names of its 139347SAndreas.Sandberg@arm.com * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A */ 282810SN/A 292810SN/A#include <cassert> 302810SN/A 312810SN/A#include "mem/protocol/MachineType.hh" 322810SN/A#include "mem/protocol/Protocol.hh" 332810SN/A#include "mem/protocol/TopologyType.hh" 342810SN/A#include "mem/ruby/common/NetDest.hh" 352810SN/A#include "mem/ruby/network/Network.hh" 362810SN/A#include "mem/ruby/network/simple/Topology.hh" 372810SN/A#include "mem/ruby/slicc_interface/AbstractController.hh" 382810SN/A#include "mem/ruby/system/System.hh" 392810SN/A 402810SN/Ausing namespace std; 419347SAndreas.Sandberg@arm.com 422810SN/Aconst int INFINITE_LATENCY = 10000; // Yes, this is a big hack 432810SN/Aconst int DEFAULT_BW_MULTIPLIER = 1; // Just to be consistent with above :) 442810SN/A 454626SN/A// Note: In this file, we use the first 2*m_nodes SwitchIDs to 462810SN/A// represent the input and output endpoint links. These really are 472810SN/A// not 'switches', as they will not have a Switch object allocated for 485338Sstever@gmail.com// them. The first m_nodes SwitchIDs are the links into the network, 492810SN/A// the second m_nodes set of SwitchIDs represent the the output queues 5012727Snikos.nikoleris@arm.com// of the network. 5112727Snikos.nikoleris@arm.com 5212727Snikos.nikoleris@arm.com// Helper functions based on chapter 29 of Cormen et al. 5312727Snikos.nikoleris@arm.comvoid extend_shortest_path(Matrix& current_dist, Matrix& latencies, 545314SN/A Matrix& inter_switches); 5511375Sandreas.hansson@arm.comMatrix shortest_path(const Matrix& weights, Matrix& latencies, 5611375Sandreas.hansson@arm.com Matrix& inter_switches); 5711375Sandreas.hansson@arm.combool link_is_shortest_path_to_node(SwitchID src, SwitchID next, 5811375Sandreas.hansson@arm.com SwitchID final, const Matrix& weights, const Matrix& dist); 594666SN/ANetDest shortest_path_to_node(SwitchID src, SwitchID next, 604626SN/A const Matrix& weights, const Matrix& dist); 6110764Sandreas.hansson@arm.com 6211197Sandreas.hansson@arm.comTopology::Topology(const Params *p) 632810SN/A : SimObject(p) 643149SN/A{ 652810SN/A m_print_config = p->print_config; 662810SN/A m_number_of_switches = p->num_int_nodes; 672810SN/A // initialize component latencies record 682810SN/A m_component_latencies.resize(0); 6911197Sandreas.hansson@arm.com m_component_inter_switches.resize(0); 702810SN/A 714666SN/A // Total nodes/controllers in network 722810SN/A // Must make sure this is called after the State Machine constructors 732810SN/A m_nodes = MachineType_base_number(MachineType_NUM); 742810SN/A assert(m_nodes > 1); 752810SN/A 762810SN/A if (m_nodes != params()->ext_links.size() && 772810SN/A m_nodes != params()->ext_links.size()) { 782810SN/A fatal("m_nodes (%d) != ext_links vector length (%d)\n", 792810SN/A m_nodes != params()->ext_links.size()); 802810SN/A } 812810SN/A 824666SN/A // First create the links between the endpoints (i.e. controllers) 834666SN/A // and the network. 842810SN/A for (vector<ExtLink*>::const_iterator i = params()->ext_links.begin(); 852810SN/A i != params()->ext_links.end(); ++i) { 862810SN/A const ExtLinkParams *p = (*i)->params(); 872810SN/A AbstractController *c = p->ext_node; 8811284Sandreas.hansson@arm.com 892810SN/A // Store the controller pointers for later 9011375Sandreas.hansson@arm.com m_controller_vector.push_back(c); 9111375Sandreas.hansson@arm.com 9211375Sandreas.hansson@arm.com int ext_idx1 = 932810SN/A MachineType_base_number(c->getMachineType()) + c->getVersion(); 942810SN/A int ext_idx2 = ext_idx1 + m_nodes; 952810SN/A int int_idx = p->int_node + 2*m_nodes; 964626SN/A 972810SN/A // create the links in both directions 984666SN/A addLink(ext_idx1, int_idx, p->latency, p->bw_multiplier, p->weight); 992810SN/A addLink(int_idx, ext_idx2, p->latency, p->bw_multiplier, p->weight); 10011375Sandreas.hansson@arm.com } 1012810SN/A 1022810SN/A for (vector<IntLink*>::const_iterator i = params()->int_links.begin(); 1032810SN/A i != params()->int_links.end(); ++i) { 1042810SN/A const IntLinkParams *p = (*i)->params(); 1054666SN/A int a = p->node_a + 2*m_nodes; 1062810SN/A int b = p->node_b + 2*m_nodes; 1072810SN/A 10810192Smitch.hayenga@arm.com // create the links in both directions 10910192Smitch.hayenga@arm.com addLink(a, b, p->latency, p->bw_multiplier, p->weight); 11010192Smitch.hayenga@arm.com addLink(b, a, p->latency, p->bw_multiplier, p->weight); 11110192Smitch.hayenga@arm.com } 11210192Smitch.hayenga@arm.com} 11310192Smitch.hayenga@arm.com 11410192Smitch.hayenga@arm.com 11510192Smitch.hayenga@arm.comvoid 11610192Smitch.hayenga@arm.comTopology::initNetworkPtr(Network* net_ptr) 11711375Sandreas.hansson@arm.com{ 11810192Smitch.hayenga@arm.com for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 11910192Smitch.hayenga@arm.com m_controller_vector[cntrl]->initNetworkPtr(net_ptr); 12010192Smitch.hayenga@arm.com } 12110192Smitch.hayenga@arm.com} 12210192Smitch.hayenga@arm.com 123void 124Topology::createLinks(Network *net, bool isReconfiguration) 125{ 126 // Find maximum switchID 127 SwitchID max_switch_id = 0; 128 for (int i = 0; i < m_links_src_vector.size(); i++) { 129 max_switch_id = max(max_switch_id, m_links_src_vector[i]); 130 max_switch_id = max(max_switch_id, m_links_dest_vector[i]); 131 } 132 133 // Initialize weight vector 134 Matrix topology_weights; 135 Matrix topology_latency; 136 Matrix topology_bw_multis; 137 int num_switches = max_switch_id+1; 138 topology_weights.resize(num_switches); 139 topology_latency.resize(num_switches); 140 topology_bw_multis.resize(num_switches); 141 142 // FIXME setting the size of a member variable here is a HACK! 143 m_component_latencies.resize(num_switches); 144 145 // FIXME setting the size of a member variable here is a HACK! 146 m_component_inter_switches.resize(num_switches); 147 148 for (int i = 0; i < topology_weights.size(); i++) { 149 topology_weights[i].resize(num_switches); 150 topology_latency[i].resize(num_switches); 151 topology_bw_multis[i].resize(num_switches); 152 m_component_latencies[i].resize(num_switches); 153 154 // FIXME setting the size of a member variable here is a HACK! 155 m_component_inter_switches[i].resize(num_switches); 156 157 for (int j = 0; j < topology_weights[i].size(); j++) { 158 topology_weights[i][j] = INFINITE_LATENCY; 159 160 // initialize to invalid values 161 topology_latency[i][j] = -1; 162 topology_bw_multis[i][j] = -1; 163 m_component_latencies[i][j] = -1; 164 165 // initially assume direct connections / no intermediate 166 // switches between components 167 m_component_inter_switches[i][j] = 0; 168 } 169 } 170 171 // Set identity weights to zero 172 for (int i = 0; i < topology_weights.size(); i++) { 173 topology_weights[i][i] = 0; 174 } 175 176 // Fill in the topology weights and bandwidth multipliers 177 for (int i = 0; i < m_links_src_vector.size(); i++) { 178 int src = m_links_src_vector[i]; 179 int dst = m_links_dest_vector[i]; 180 topology_weights[src][dst] = m_links_weight_vector[i]; 181 topology_latency[src][dst] = m_links_latency_vector[i]; 182 m_component_latencies[src][dst] = m_links_latency_vector[i]; 183 topology_bw_multis[src][dst] = m_bw_multiplier_vector[i]; 184 } 185 186 // Walk topology and hookup the links 187 Matrix dist = shortest_path(topology_weights, m_component_latencies, 188 m_component_inter_switches); 189 for (int i = 0; i < topology_weights.size(); i++) { 190 for (int j = 0; j < topology_weights[i].size(); j++) { 191 int weight = topology_weights[i][j]; 192 int bw_multiplier = topology_bw_multis[i][j]; 193 int latency = topology_latency[i][j]; 194 if (weight > 0 && weight != INFINITE_LATENCY) { 195 NetDest destination_set = shortest_path_to_node(i, j, 196 topology_weights, dist); 197 assert(latency != -1); 198 makeLink(net, i, j, destination_set, latency, weight, 199 bw_multiplier, isReconfiguration); 200 } 201 } 202 } 203} 204 205SwitchID 206Topology::newSwitchID() 207{ 208 m_number_of_switches++; 209 return m_number_of_switches-1+m_nodes+m_nodes; 210} 211 212void 213Topology::addLink(SwitchID src, SwitchID dest, int link_latency) 214{ 215 addLink(src, dest, link_latency, DEFAULT_BW_MULTIPLIER, link_latency); 216} 217 218void 219Topology::addLink(SwitchID src, SwitchID dest, int link_latency, 220 int bw_multiplier) 221{ 222 addLink(src, dest, link_latency, bw_multiplier, link_latency); 223} 224 225void 226Topology::addLink(SwitchID src, SwitchID dest, int link_latency, 227 int bw_multiplier, int link_weight) 228{ 229 assert(src <= m_number_of_switches+m_nodes+m_nodes); 230 assert(dest <= m_number_of_switches+m_nodes+m_nodes); 231 m_links_src_vector.push_back(src); 232 m_links_dest_vector.push_back(dest); 233 m_links_latency_vector.push_back(link_latency); 234 m_links_weight_vector.push_back(link_weight); 235 m_bw_multiplier_vector.push_back(bw_multiplier); 236} 237 238void 239Topology::makeLink(Network *net, SwitchID src, SwitchID dest, 240 const NetDest& routing_table_entry, int link_latency, int link_weight, 241 int bw_multiplier, bool isReconfiguration) 242{ 243 // Make sure we're not trying to connect two end-point nodes 244 // directly together 245 assert(src >= 2 * m_nodes || dest >= 2 * m_nodes); 246 247 if (src < m_nodes) { 248 net->makeInLink(src, dest-(2*m_nodes), routing_table_entry, 249 link_latency, bw_multiplier, isReconfiguration); 250 } else if (dest < 2*m_nodes) { 251 assert(dest >= m_nodes); 252 NodeID node = dest-m_nodes; 253 net->makeOutLink(src-(2*m_nodes), node, routing_table_entry, 254 link_latency, link_weight, bw_multiplier, isReconfiguration); 255 } else { 256 assert((src >= 2*m_nodes) && (dest >= 2*m_nodes)); 257 net->makeInternalLink(src-(2*m_nodes), dest-(2*m_nodes), 258 routing_table_entry, link_latency, link_weight, bw_multiplier, 259 isReconfiguration); 260 } 261} 262 263void 264Topology::printStats(std::ostream& out) const 265{ 266 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 267 m_controller_vector[cntrl]->printStats(out); 268 } 269} 270 271void 272Topology::clearStats() 273{ 274 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 275 m_controller_vector[cntrl]->clearStats(); 276 } 277} 278 279void 280Topology::printConfig(std::ostream& out) const 281{ 282 if (m_print_config == false) 283 return; 284 285 assert(m_component_latencies.size() > 0); 286 287 out << "--- Begin Topology Print ---" << endl 288 << endl 289 << "Topology print ONLY indicates the _NETWORK_ latency between two " 290 << "machines" << endl 291 << "It does NOT include the latency within the machines" << endl 292 << endl; 293 294 for (int m = 0; m < MachineType_NUM; m++) { 295 int i_end = MachineType_base_count((MachineType)m); 296 for (int i = 0; i < i_end; i++) { 297 MachineID cur_mach = {(MachineType)m, i}; 298 out << cur_mach << " Network Latencies" << endl; 299 for (int n = 0; n < MachineType_NUM; n++) { 300 int j_end = MachineType_base_count((MachineType)n); 301 for (int j = 0; j < j_end; j++) { 302 MachineID dest_mach = {(MachineType)n, j}; 303 if (cur_mach == dest_mach) 304 continue; 305 306 int src = MachineType_base_number((MachineType)m) + i; 307 int dst = MachineType_base_number(MachineType_NUM) + 308 MachineType_base_number((MachineType)n) + j; 309 int link_latency = m_component_latencies[src][dst]; 310 int intermediate_switches = 311 m_component_inter_switches[src][dst]; 312 313 // NOTE switches are assumed to have single 314 // cycle latency 315 out << " " << cur_mach << " -> " << dest_mach 316 << " net_lat: " 317 << link_latency + intermediate_switches << endl; 318 } 319 } 320 out << endl; 321 } 322 } 323 324 out << "--- End Topology Print ---" << endl; 325} 326 327// The following all-pairs shortest path algorithm is based on the 328// discussion from Cormen et al., Chapter 26.1. 329void 330extend_shortest_path(Matrix& current_dist, Matrix& latencies, 331 Matrix& inter_switches) 332{ 333 bool change = true; 334 int nodes = current_dist.size(); 335 336 while (change) { 337 change = false; 338 for (int i = 0; i < nodes; i++) { 339 for (int j = 0; j < nodes; j++) { 340 int minimum = current_dist[i][j]; 341 int previous_minimum = minimum; 342 int intermediate_switch = -1; 343 for (int k = 0; k < nodes; k++) { 344 minimum = min(minimum, 345 current_dist[i][k] + current_dist[k][j]); 346 if (previous_minimum != minimum) { 347 intermediate_switch = k; 348 inter_switches[i][j] = 349 inter_switches[i][k] + 350 inter_switches[k][j] + 1; 351 } 352 previous_minimum = minimum; 353 } 354 if (current_dist[i][j] != minimum) { 355 change = true; 356 current_dist[i][j] = minimum; 357 assert(intermediate_switch >= 0); 358 assert(intermediate_switch < latencies[i].size()); 359 latencies[i][j] = latencies[i][intermediate_switch] + 360 latencies[intermediate_switch][j]; 361 } 362 } 363 } 364 } 365} 366 367Matrix 368shortest_path(const Matrix& weights, Matrix& latencies, Matrix& inter_switches) 369{ 370 Matrix dist = weights; 371 extend_shortest_path(dist, latencies, inter_switches); 372 return dist; 373} 374 375bool 376link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final, 377 const Matrix& weights, const Matrix& dist) 378{ 379 return weights[src][next] + dist[next][final] == dist[src][final]; 380} 381 382NetDest 383shortest_path_to_node(SwitchID src, SwitchID next, const Matrix& weights, 384 const Matrix& dist) 385{ 386 NetDest result; 387 int d = 0; 388 int machines; 389 int max_machines; 390 391 machines = MachineType_NUM; 392 max_machines = MachineType_base_number(MachineType_NUM); 393 394 for (int m = 0; m < machines; m++) { 395 for (int i = 0; i < MachineType_base_count((MachineType)m); i++) { 396 // we use "d+max_machines" below since the "destination" 397 // switches for the machines are numbered 398 // [MachineType_base_number(MachineType_NUM)... 399 // 2*MachineType_base_number(MachineType_NUM)-1] for the 400 // component network 401 if (link_is_shortest_path_to_node(src, next, d + max_machines, 402 weights, dist)) { 403 MachineID mach = {(MachineType)m, i}; 404 result.add(mach); 405 } 406 d++; 407 } 408 } 409 410 DPRINTF(RubyNetwork, "Returning shortest path\n" 411 "(src-(2*max_machines)): %d, (next-(2*max_machines)): %d, " 412 "src: %d, next: %d, result: %s\n", 413 (src-(2*max_machines)), (next-(2*max_machines)), 414 src, next, result); 415 416 return result; 417} 418 419Topology * 420TopologyParams::create() 421{ 422 return new Topology(this); 423} 424 425Link * 426LinkParams::create() 427{ 428 return new Link(this); 429} 430 431ExtLink * 432ExtLinkParams::create() 433{ 434 return new ExtLink(this); 435} 436 437IntLink * 438IntLinkParams::create() 439{ 440 return new IntLink(this); 441} 442