Topology.cc revision 6895
11689SN/A 22326SN/A/* 31689SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu */ 292831Sksewell@umich.edu 301689SN/A/* 311689SN/A * Topology.cc 322064SN/A * 331060SN/A * Description: See Topology.hh 341060SN/A * 351696SN/A * $Id$ 361689SN/A * 372292SN/A * */ 381717SN/A 391060SN/A#include "mem/ruby/network/simple/Topology.hh" 401061SN/A#include "mem/ruby/common/NetDest.hh" 412292SN/A#include "mem/ruby/network/Network.hh" 422292SN/A#include "mem/ruby/slicc_interface/AbstractController.hh" 432292SN/A#include "mem/protocol/TopologyType.hh" 442292SN/A#include "mem/gems_common/util.hh" 452326SN/A#include "mem/protocol/MachineType.hh" 461060SN/A#include "mem/protocol/Protocol.hh" 472292SN/A#include "mem/ruby/system/System.hh" 482292SN/A#include <string> 492292SN/A 502292SN/Astatic const int INFINITE_LATENCY = 10000; // Yes, this is a big hack 512292SN/Astatic const int DEFAULT_BW_MULTIPLIER = 1; // Just to be consistent with above :) 522292SN/A 532292SN/A// Note: In this file, we use the first 2*m_nodes SwitchIDs to 542326SN/A// represent the input and output endpoint links. These really are 552292SN/A// not 'switches', as they will not have a Switch object allocated for 562292SN/A// them. The first m_nodes SwitchIDs are the links into the network, 572292SN/A// the second m_nodes set of SwitchIDs represent the the output queues 582292SN/A// of the network. 592292SN/A 602292SN/A// Helper functions based on chapter 29 of Cormen et al. 612292SN/Astatic void extend_shortest_path(Matrix& current_dist, Matrix& latencies, Matrix& inter_switches); 622292SN/Astatic Matrix shortest_path(const Matrix& weights, Matrix& latencies, Matrix& inter_switches); 632292SN/Astatic bool link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final, const Matrix& weights, const Matrix& dist); 642292SN/Astatic NetDest shortest_path_to_node(SwitchID src, SwitchID next, const Matrix& weights, const Matrix& dist); 652292SN/A 662292SN/ATopology::Topology(const Params *p) 672292SN/A : SimObject(p) 682669Sktlim@umich.edu{ 692292SN/A m_print_config = p->print_config; 702292SN/A m_number_of_switches = p->num_int_nodes; 712292SN/A // initialize component latencies record 722292SN/A m_component_latencies.setSize(0); 732292SN/A m_component_inter_switches.setSize(0); 742292SN/A 752292SN/A // 762292SN/A // Total nodes/controllers in network 772307SN/A // Must make sure this is called after the State Machine constructors 782307SN/A // 792292SN/A m_nodes = MachineType_base_number(MachineType_NUM); 801060SN/A assert(m_nodes > 1); 811060SN/A 821060SN/A if (m_nodes != params()->ext_links.size()) { 831060SN/A fatal("m_nodes (%d) != ext_links vector length (%d)\n", 842292SN/A m_nodes != params()->ext_links.size()); 851060SN/A } 861060SN/A 871060SN/A // 882326SN/A // First create the links between the endpoints (i.e. controllers) and the 891060SN/A // network. 901060SN/A // 911060SN/A for (vector<ExtLink*>::const_iterator i = params()->ext_links.begin(); 921060SN/A i != params()->ext_links.end(); ++i) 932292SN/A { 942292SN/A const ExtLinkParams *p = (*i)->params(); 952292SN/A AbstractController *c = p->ext_node; 962292SN/A 971060SN/A // Store the controller pointers for later 981060SN/A m_controller_vector.insertAtBottom(c); 992307SN/A 1002292SN/A int ext_idx1 = 1012980Sgblack@eecs.umich.edu MachineType_base_number(c->getMachineType()) + c->getVersion(); 1022292SN/A int ext_idx2 = ext_idx1 + m_nodes; 1032292SN/A int int_idx = p->int_node + 2*m_nodes; 1042292SN/A 1052292SN/A // create the links in both directions 1062292SN/A addLink(ext_idx1, int_idx, p->latency, p->bw_multiplier, p->weight); 1072292SN/A addLink(int_idx, ext_idx2, p->latency, p->bw_multiplier, p->weight); 1082292SN/A } 1092292SN/A 1102292SN/A for (vector<IntLink*>::const_iterator i = params()->int_links.begin(); 1112292SN/A i != params()->int_links.end(); ++i) 1122292SN/A { 1132292SN/A const IntLinkParams *p = (*i)->params(); 1142292SN/A int a = p->node_a + 2*m_nodes; 1152292SN/A int b = p->node_b + 2*m_nodes; 1162292SN/A 1172292SN/A // create the links in both directions 1182292SN/A addLink(a, b, p->latency, p->bw_multiplier, p->weight); 1192292SN/A addLink(b, a, p->latency, p->bw_multiplier, p->weight); 1202292SN/A } 1212292SN/A} 1222292SN/A 1232292SN/A 1242292SN/Avoid Topology::initNetworkPtr(Network* net_ptr) 1252292SN/A{ 1262292SN/A for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) 1272831Sksewell@umich.edu { 1282292SN/A m_controller_vector[cntrl]->initNetworkPtr(net_ptr); 1292292SN/A } 1302292SN/A} 1312292SN/A 1322292SN/A 1332292SN/Avoid Topology::createLinks(Network *net, bool isReconfiguration) 1342292SN/A{ 1352292SN/A // Find maximum switchID 1362292SN/A 1372292SN/A SwitchID max_switch_id = 0; 1382292SN/A for (int i=0; i<m_links_src_vector.size(); i++) { 1392292SN/A max_switch_id = max(max_switch_id, m_links_src_vector[i]); 1402292SN/A max_switch_id = max(max_switch_id, m_links_dest_vector[i]); 1412292SN/A } 1422831Sksewell@umich.edu 1432292SN/A // Initialize weight vector 1442292SN/A Matrix topology_weights; 1452292SN/A Matrix topology_latency; 1462292SN/A Matrix topology_bw_multis; 1472292SN/A int num_switches = max_switch_id+1; 1482292SN/A topology_weights.setSize(num_switches); 1492292SN/A topology_latency.setSize(num_switches); 1502292SN/A topology_bw_multis.setSize(num_switches); 1512292SN/A m_component_latencies.setSize(num_switches); // FIXME setting the size of a member variable here is a HACK! 1522292SN/A m_component_inter_switches.setSize(num_switches); // FIXME setting the size of a member variable here is a HACK! 1532326SN/A for(int i=0; i<topology_weights.size(); i++) { 1542348SN/A topology_weights[i].setSize(num_switches); 1552326SN/A topology_latency[i].setSize(num_switches); 1562326SN/A topology_bw_multis[i].setSize(num_switches); 1572348SN/A m_component_latencies[i].setSize(num_switches); 1582292SN/A m_component_inter_switches[i].setSize(num_switches); // FIXME setting the size of a member variable here is a HACK! 1592292SN/A for(int j=0; j<topology_weights[i].size(); j++) { 1602292SN/A topology_weights[i][j] = INFINITE_LATENCY; 1612292SN/A topology_latency[i][j] = -1; // initialize to an invalid value 1622292SN/A topology_bw_multis[i][j] = -1; // initialize to an invalid value 1632292SN/A m_component_latencies[i][j] = -1; // initialize to an invalid value 1642292SN/A m_component_inter_switches[i][j] = 0; // initially assume direct connections / no intermediate switches between components 1651060SN/A } 1661060SN/A } 1671061SN/A 1681060SN/A // Set identity weights to zero 1691062SN/A for(int i=0; i<topology_weights.size(); i++) { 1701062SN/A topology_weights[i][i] = 0; 1712301SN/A } 1721062SN/A 1731062SN/A // Fill in the topology weights and bandwidth multipliers 1741062SN/A for (int i=0; i<m_links_src_vector.size(); i++) { 1751062SN/A topology_weights[m_links_src_vector[i]][m_links_dest_vector[i]] = m_links_weight_vector[i]; 1761062SN/A topology_latency[m_links_src_vector[i]][m_links_dest_vector[i]] = m_links_latency_vector[i]; 1771062SN/A m_component_latencies[m_links_src_vector[i]][m_links_dest_vector[i]] = m_links_latency_vector[i]; // initialize to latency vector 1781062SN/A topology_bw_multis[m_links_src_vector[i]][m_links_dest_vector[i]] = m_bw_multiplier_vector[i]; 1791062SN/A } 1801062SN/A 1811062SN/A // Walk topology and hookup the links 1822301SN/A Matrix dist = shortest_path(topology_weights, m_component_latencies, m_component_inter_switches); 1832301SN/A for(int i=0; i<topology_weights.size(); i++) { 1842301SN/A for(int j=0; j<topology_weights[i].size(); j++) { 1852301SN/A int weight = topology_weights[i][j]; 1861062SN/A int bw_multiplier = topology_bw_multis[i][j]; 1871062SN/A int latency = topology_latency[i][j]; 1881062SN/A if (weight > 0 && weight != INFINITE_LATENCY) { 1891062SN/A NetDest destination_set = shortest_path_to_node(i, j, topology_weights, dist); 1901062SN/A assert(latency != -1); 1911062SN/A makeLink(net, i, j, destination_set, latency, weight, bw_multiplier, isReconfiguration); 1921062SN/A } 1931062SN/A } 1941062SN/A } 1951062SN/A} 1961062SN/A 1971062SN/ASwitchID Topology::newSwitchID() 1981062SN/A{ 1991062SN/A m_number_of_switches++; 2001062SN/A return m_number_of_switches-1+m_nodes+m_nodes; 2011062SN/A} 2021062SN/A 2031062SN/Avoid Topology::addLink(SwitchID src, SwitchID dest, int link_latency) 2041062SN/A{ 2051062SN/A addLink(src, dest, link_latency, DEFAULT_BW_MULTIPLIER, link_latency); 2061062SN/A} 2071062SN/A 2081062SN/Avoid Topology::addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier) 2091062SN/A{ 2101062SN/A addLink(src, dest, link_latency, bw_multiplier, link_latency); 2111062SN/A} 2121062SN/A 2131062SN/Avoid Topology::addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier, int link_weight) 2141062SN/A{ 2151062SN/A ASSERT(src <= m_number_of_switches+m_nodes+m_nodes); 2161062SN/A ASSERT(dest <= m_number_of_switches+m_nodes+m_nodes); 2171062SN/A m_links_src_vector.insertAtBottom(src); 2181062SN/A m_links_dest_vector.insertAtBottom(dest); 2191062SN/A m_links_latency_vector.insertAtBottom(link_latency); 2201062SN/A m_links_weight_vector.insertAtBottom(link_weight); 2211062SN/A m_bw_multiplier_vector.insertAtBottom(bw_multiplier); 2221062SN/A} 2231062SN/A 2241062SN/Avoid Topology::makeLink(Network *net, SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration) 2251062SN/A{ 2261062SN/A // Make sure we're not trying to connect two end-point nodes directly together 2271062SN/A assert((src >= 2*m_nodes) || (dest >= 2*m_nodes)); 2281062SN/A 2291062SN/A if (src < m_nodes) { 2301062SN/A net->makeInLink(src, dest-(2*m_nodes), routing_table_entry, link_latency, bw_multiplier, isReconfiguration); 2311062SN/A } else if (dest < 2*m_nodes) { 2321062SN/A assert(dest >= m_nodes); 2331062SN/A NodeID node = dest-m_nodes; 2342326SN/A net->makeOutLink(src-(2*m_nodes), node, routing_table_entry, link_latency, link_weight, bw_multiplier, isReconfiguration); 2352301SN/A } else { 2362301SN/A assert((src >= 2*m_nodes) && (dest >= 2*m_nodes)); 2372301SN/A net->makeInternalLink(src-(2*m_nodes), dest-(2*m_nodes), routing_table_entry, link_latency, link_weight, bw_multiplier, isReconfiguration); 2382301SN/A } 2392301SN/A} 2402301SN/A 2412326SN/Avoid Topology::printStats(ostream& out) const 2422301SN/A{ 2432326SN/A for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 2442307SN/A m_controller_vector[cntrl]->printStats(out); 2452301SN/A } 2462301SN/A} 2472307SN/A 2482301SN/Avoid Topology::clearStats() 2492301SN/A{ 2502301SN/A for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 2512301SN/A m_controller_vector[cntrl]->clearStats(); 2522301SN/A } 2532301SN/A} 2542301SN/A 2552301SN/Avoid Topology::printConfig(ostream& out) const 2562301SN/A{ 2572301SN/A if (m_print_config == false) return; 2582301SN/A 2592301SN/A assert(m_component_latencies.size() > 0); 2602326SN/A 2612301SN/A out << "--- Begin Topology Print ---" << endl; 2622301SN/A out << endl; 2632301SN/A out << "Topology print ONLY indicates the _NETWORK_ latency between two machines" << endl; 2642301SN/A out << "It does NOT include the latency within the machines" << endl; 2652301SN/A out << endl; 2662326SN/A for (int m=0; m<MachineType_NUM; m++) { 2672301SN/A for (int i=0; i<MachineType_base_count((MachineType)m); i++) { 2682301SN/A MachineID cur_mach = {(MachineType)m, i}; 2692301SN/A out << cur_mach << " Network Latencies" << endl; 2702301SN/A for (int n=0; n<MachineType_NUM; n++) { 2712301SN/A for (int j=0; j<MachineType_base_count((MachineType)n); j++) { 2722326SN/A MachineID dest_mach = {(MachineType)n, j}; 2732301SN/A if (cur_mach != dest_mach) { 2742301SN/A int link_latency = m_component_latencies[MachineType_base_number((MachineType)m)+i][MachineType_base_number(MachineType_NUM)+MachineType_base_number((MachineType)n)+j]; 2752301SN/A int intermediate_switches = m_component_inter_switches[MachineType_base_number((MachineType)m)+i][MachineType_base_number(MachineType_NUM)+MachineType_base_number((MachineType)n)+j]; 2762301SN/A out << " " << cur_mach << " -> " << dest_mach << " net_lat: " 2772301SN/A << link_latency+intermediate_switches << endl; // NOTE switches are assumed to have single cycle latency 2782301SN/A } 2792301SN/A } 2802980Sgblack@eecs.umich.edu } 2812301SN/A out << endl; 2822326SN/A } 2832301SN/A } 2842301SN/A 2852326SN/A out << "--- End Topology Print ---" << endl; 2862301SN/A} 2872301SN/A 2882301SN/A/**************************************************************************/ 2892301SN/A 2902326SN/A// The following all-pairs shortest path algorithm is based on the 2912727Sktlim@umich.edu// discussion from Cormen et al., Chapter 26.1. 2922326SN/A 2932301SN/Astatic void extend_shortest_path(Matrix& current_dist, Matrix& latencies, Matrix& inter_switches) 2942301SN/A{ 2952301SN/A bool change = true; 2962301SN/A int nodes = current_dist.size(); 2972301SN/A 2982301SN/A while (change) { 2992326SN/A change = false; 3002301SN/A for (int i=0; i<nodes; i++) { 3012301SN/A for (int j=0; j<nodes; j++) { 3022326SN/A int minimum = current_dist[i][j]; 3032301SN/A int previous_minimum = minimum; 3042301SN/A int intermediate_switch = -1; 3052301SN/A for (int k=0; k<nodes; k++) { 3062301SN/A minimum = min(minimum, current_dist[i][k] + current_dist[k][j]); 3072301SN/A if (previous_minimum != minimum) { 3082301SN/A intermediate_switch = k; 3092326SN/A inter_switches[i][j] = inter_switches[i][k] + inter_switches[k][j] + 1; 3102301SN/A } 3112301SN/A previous_minimum = minimum; 3122301SN/A } 3132301SN/A if (current_dist[i][j] != minimum) { 3142326SN/A change = true; 3152301SN/A current_dist[i][j] = minimum; 3162292SN/A assert(intermediate_switch >= 0); 3172292SN/A assert(intermediate_switch < latencies[i].size()); 3182292SN/A latencies[i][j] = latencies[i][intermediate_switch] + latencies[intermediate_switch][j]; 3192292SN/A } 3201062SN/A } 3211062SN/A } 3221062SN/A } 3231062SN/A} 3242307SN/A 3251060SN/Astatic Matrix shortest_path(const Matrix& weights, Matrix& latencies, Matrix& inter_switches) 3262307SN/A{ 3272307SN/A Matrix dist = weights; 3282307SN/A extend_shortest_path(dist, latencies, inter_switches); 3292307SN/A return dist; 3302307SN/A} 3311060SN/A 3322307SN/Astatic bool link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final, 3332307SN/A const Matrix& weights, const Matrix& dist) 3342307SN/A{ 3352307SN/A return (weights[src][next] + dist[next][final] == dist[src][final]); 3362307SN/A} 3372307SN/A 3382307SN/Astatic NetDest shortest_path_to_node(SwitchID src, SwitchID next, 3392307SN/A const Matrix& weights, const Matrix& dist) 3402307SN/A{ 3412307SN/A NetDest result; 3422307SN/A int d = 0; 3432307SN/A int machines; 3442307SN/A int max_machines; 3452307SN/A 3462307SN/A machines = MachineType_NUM; 3472307SN/A max_machines = MachineType_base_number(MachineType_NUM); 3482307SN/A 3492307SN/A for (int m=0; m<machines; m++) { 3502307SN/A for (int i=0; i<MachineType_base_count((MachineType)m); i++) { 3512307SN/A // we use "d+max_machines" below since the "destination" switches for the machines are numbered 3522307SN/A // [MachineType_base_number(MachineType_NUM)...2*MachineType_base_number(MachineType_NUM)-1] 3532307SN/A // for the component network 3542307SN/A if (link_is_shortest_path_to_node(src, next, 3552307SN/A d+max_machines, 3561060SN/A weights, dist)) { 3571060SN/A MachineID mach = {(MachineType)m, i}; 3581061SN/A result.add(mach); 3591060SN/A } 3602980Sgblack@eecs.umich.edu d++; 3611060SN/A } 3622292SN/A } 3632292SN/A 3642064SN/A DEBUG_MSG(NETWORK_COMP, MedPrio, "returning shortest path"); 3652064SN/A DEBUG_EXPR(NETWORK_COMP, MedPrio, (src-(2*max_machines))); 3662064SN/A DEBUG_EXPR(NETWORK_COMP, MedPrio, (next-(2*max_machines))); 3672064SN/A DEBUG_EXPR(NETWORK_COMP, MedPrio, src); 3682292SN/A DEBUG_EXPR(NETWORK_COMP, MedPrio, next); 3692064SN/A DEBUG_EXPR(NETWORK_COMP, MedPrio, result); 3702292SN/A DEBUG_NEWLINE(NETWORK_COMP, MedPrio); 3711060SN/A 3721060SN/A return result; 3731060SN/A} 3741061SN/A 3751060SN/ATopology * 3761060SN/ATopologyParams::create() 3771060SN/A{ 3782292SN/A return new Topology(this); 3791060SN/A} 3801060SN/A 3811060SN/ALink * 3821060SN/ALinkParams::create() 3831060SN/A{ 3841684SN/A return new Link(this); 3852307SN/A} 3862307SN/A 3872307SN/AExtLink * 3882307SN/AExtLinkParams::create() 3892326SN/A{ 3902307SN/A return new ExtLink(this); 3912307SN/A} 3922307SN/A 3932307SN/AIntLink * 3942307SN/AIntLinkParams::create() 3952307SN/A{ 3962307SN/A return new IntLink(this); 3972307SN/A} 3982307SN/A