Network.hh revision 9302:c2e70a9bc340
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 * The Network class is the base class for classes that implement the 31 * interconnection network between components (processor/cache 32 * components and memory/directory components). The interconnection 33 * network as described here is not a physical network, but a 34 * programming concept used to implement all communication between 35 * components. Thus parts of this 'network' will model the on-chip 36 * connections between cache controllers and directory controllers as 37 * well as the links between chip and network switches. 38 */ 39 40#ifndef __MEM_RUBY_NETWORK_NETWORK_HH__ 41#define __MEM_RUBY_NETWORK_NETWORK_HH__ 42 43#include <iostream> 44#include <string> 45#include <vector> 46 47#include "mem/packet.hh" 48#include "mem/protocol/LinkDirection.hh" 49#include "mem/protocol/MessageSizeType.hh" 50#include "mem/ruby/common/TypeDefines.hh" 51#include "params/RubyNetwork.hh" 52#include "sim/sim_object.hh" 53 54class NetDest; 55class MessageBuffer; 56class Throttle; 57class Topology; 58 59class Network : public SimObject 60{ 61 public: 62 typedef RubyNetworkParams Params; 63 Network(const Params *p); 64 virtual ~Network() {} 65 66 virtual void init(); 67 68 static int getNumberOfVirtualNetworks() { return m_virtual_networks; } 69 static uint32_t MessageSizeType_to_int(MessageSizeType size_type); 70 71 // returns the queue requested for the given component 72 virtual MessageBuffer* getToNetQueue(NodeID id, bool ordered, 73 int netNumber, std::string vnet_type) = 0; 74 virtual MessageBuffer* getFromNetQueue(NodeID id, bool ordered, 75 int netNumber, std::string vnet_type) = 0; 76 virtual const std::vector<Throttle*>* getThrottles(NodeID id) const; 77 virtual int getNumNodes() {return 1;} 78 79 virtual void makeOutLink(SwitchID src, NodeID dest, BasicLink* link, 80 LinkDirection direction, 81 const NetDest& routing_table_entry, 82 bool isReconfiguration) = 0; 83 virtual void makeInLink(NodeID src, SwitchID dest, BasicLink* link, 84 LinkDirection direction, 85 const NetDest& routing_table_entry, 86 bool isReconfiguration) = 0; 87 virtual void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, 88 LinkDirection direction, 89 const NetDest& routing_table_entry, 90 bool isReconfiguration) = 0; 91 92 virtual void reset() = 0; 93 94 virtual void printStats(std::ostream& out) const = 0; 95 virtual void clearStats() = 0; 96 virtual void print(std::ostream& out) const = 0; 97 98 /* 99 * Virtual functions for functionally reading and writing packets in 100 * the network. Each network needs to implement these for functional 101 * accesses to work correctly. 102 */ 103 virtual bool functionalRead(Packet *pkt) 104 { fatal("Functional read not implemented.\n"); } 105 virtual uint32_t functionalWrite(Packet *pkt) 106 { fatal("Functional write not implemented.\n"); } 107 108 protected: 109 // Private copy constructor and assignment operator 110 Network(const Network& obj); 111 Network& operator=(const Network& obj); 112 113 protected: 114 const std::string m_name; 115 int m_nodes; 116 static uint32_t m_virtual_networks; 117 Topology* m_topology_ptr; 118 static uint32_t m_control_msg_size; 119 static uint32_t m_data_msg_size; 120}; 121 122inline std::ostream& 123operator<<(std::ostream& out, const Network& obj) 124{ 125 obj.print(out); 126 out << std::flush; 127 return out; 128} 129 130#endif // __MEM_RUBY_NETWORK_NETWORK_HH__ 131