Network.hh revision 8259:36987780169e 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The Network class is the base class for classes that implement the
31 * interconnection network between components (processor/cache
32 * components and memory/directory components).  The interconnection
33 * network as described here is not a physical network, but a
34 * programming concept used to implement all communication between
35 * components.  Thus parts of this 'network' will model the on-chip
36 * connections between cache controllers and directory controllers as
37 * well as the links between chip and network switches.
38 */
39
40#ifndef __MEM_RUBY_NETWORK_NETWORK_HH__
41#define __MEM_RUBY_NETWORK_NETWORK_HH__
42
43#include <iostream>
44#include <string>
45#include <vector>
46
47#include "mem/protocol/LinkDirection.hh"
48#include "mem/protocol/MessageSizeType.hh"
49#include "mem/ruby/common/Global.hh"
50#include "mem/ruby/system/NodeID.hh"
51#include "mem/ruby/system/System.hh"
52#include "params/RubyNetwork.hh"
53#include "sim/sim_object.hh"
54
55class NetDest;
56class MessageBuffer;
57class Throttle;
58class Topology;
59
60class Network : public SimObject
61{
62  public:
63    typedef RubyNetworkParams Params;
64    Network(const Params *p);
65    virtual ~Network() {}
66
67    virtual void init();
68
69    int getNumberOfVirtualNetworks() { return m_virtual_networks; }
70    int getLinkLatency() { return m_link_latency; }
71    int MessageSizeType_to_int(MessageSizeType size_type);
72
73    // returns the queue requested for the given component
74    virtual MessageBuffer* getToNetQueue(NodeID id, bool ordered,
75        int netNumber) = 0;
76    virtual MessageBuffer* getFromNetQueue(NodeID id, bool ordered,
77        int netNumber) = 0;
78    virtual const std::vector<Throttle*>* getThrottles(NodeID id) const;
79    virtual int getNumNodes() {return 1;}
80
81    virtual void makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
82                             LinkDirection direction,
83                             const NetDest& routing_table_entry,
84                             bool isReconfiguration) = 0;
85    virtual void makeInLink(NodeID src, SwitchID dest, BasicLink* link,
86                            LinkDirection direction,
87                            const NetDest& routing_table_entry,
88                            bool isReconfiguration) = 0;
89    virtual void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
90                                  LinkDirection direction,
91                                  const NetDest& routing_table_entry,
92                                  bool isReconfiguration) = 0;
93
94    virtual void reset() = 0;
95
96    virtual void printStats(std::ostream& out) const = 0;
97    virtual void clearStats() = 0;
98    virtual void printConfig(std::ostream& out) const = 0;
99    virtual void print(std::ostream& out) const = 0;
100
101  protected:
102    // Private copy constructor and assignment operator
103    Network(const Network& obj);
104    Network& operator=(const Network& obj);
105
106  protected:
107    const std::string m_name;
108    int m_nodes;
109    int m_virtual_networks;
110    Topology* m_topology_ptr;
111    int m_link_latency;
112    int m_control_msg_size;
113    int m_data_msg_size;
114};
115
116inline std::ostream&
117operator<<(std::ostream& out, const Network& obj)
118{
119    obj.print(out);
120    out << std::flush;
121    return out;
122}
123
124#endif // __MEM_RUBY_NETWORK_NETWORK_HH__
125